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| PRELIMINARY NOVEMBER 2003 XRT83SL314 REV. P1.0.5 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT GENERAL DESCRIPTION The XRT83SL314 is a fully integrated 14-channel short-haul line interface unit (LIU) that operates from a single 3.3V power supply. Using internal termination, the LIU provides one bill of materials to operate in T1, E1, or J1 mode independently on a per channel basis with minimum external components. The LIU features are programmed through a standard microprocessor interface. EXAR's LIU has patented high impedance circuits that allow the transmitter outputs and receiver inputs to be high impedance when experiencing a power failure or when the LIU is powered off. Key design features within the LIU optimize 1:1 or 1+1 redundancy and non-intrusive monitoring applications to ensure reliability without using relays. The on-chip clock synthesizer generates T1/E1/J1 clock rates from a selectable external clock frequency and has five output clock references that can be used for external timing (8kHz, 1.544Mhz, 2.048Mhz, nxT1/ J1, nxE1). FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL314 Additional features include RLOS, a 16-bit LCV counter for each channel, AIS, QRSS generation/ detection, Network Loop Code generation/detection, TAOS, DMO, and diagnostic loopback modes. APPLICATIONS * * * * * * * * * * T1 Digital Cross Connects (DSX-1) ISDN Primary Rate Interface CSU/DSU E1/T1/J1 Interface T1/E1/J1 LAN/WAN Routers Public Switching Systems and PBX Interfaces T1/E1/J1 Multiplexer and Channel Banks Integrated Multi-Service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse Multiplexing for ATM (IMA) Wireless Base Stations 1 of 14 Channels NLCD Generation Driver Monitor TCLK TPOS TNEG HDB3/B8ZS Encoder Tx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen Line Driver TTIP TRING Analog Loopback Remote Loopback Digital Loopback QRSS Generation & Detection RCLK RPOS RNEG HDB3/B8ZS Decoder Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer Rx Equalizer RTIP RRING Rx Equalizer Control NLCD Detection AIS & LOS Detector DMO RLOS ICT TEST Test Microprocessor Interface Programmable Master Clock Synthesizer 8kHzOUT MCLKE1out MCLKT1out MCLKE1Nout MCLKT1Nout RxON RxTSEL [10:0] [7:0] TxON uPCLK uPTS2 uPTS1 uPTS0 CS[5:1] RDY_TA RD_WE WR_R/W Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com MCLKin ADDR CS ALE DATA Reset INT XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY * Receiver line attenuation indication output in 1dB steps. and E1 (2.048MHz) FEATURES * Fully integrated 14-Channel short haul transceivers for T1/J1 (1.544MHz) applications. * Loss of signal (RLOS) according to ITU-T G.775/ ETS300233 (E1) and ANSI T1.403 (T1/J1). * T1/E1/J1 short haul and clock rate are per port selectable through software without changing components. * Programmable receive slicer threshold (45%, 50%, 55%, or 68%) for improved receiver interference immunity. * Internal Impedance matching on both receive and transmit for 75 (E1), 100 (T1), 110 (J1), and 120 (E1) applications are per port selectable through software without changing components. * Programmable data stream muting upon RLOS detection. * On-Chip HDB3/B8ZS encoder/decoder with an internal 16-bit LCV counter for each channel. * Power down on a per channel basis with independent receive and transmit selection. * On-Chip digital clock recovery circuit for high input jitter tolerance. * Five pre-programmed transmit pulse settings for T1 short haul applications. * QRSS pattern generator and detection for testing and monitoring. * Arbitrary Pulse Generators for both T1 and E1 modes. * On-Chip transmit short-circuit protection and limiting protects line drivers from damage on a per channel basis. * Error and bipolar violation insertion and detection. * Transmit all ones (TAOS) and in-band network loop up and loop down code generation. * Automatic loop code detection for remote loopback activation. * Independent Crystal-Less digital jitter attenuators (JA) with 32-Bit or 64-Bit FIFO for the receive and transmit paths * Supports local analog, remote, digital, and dual loopback modes. * On-Chip frequency multiplier generates T1 or E1 master clocks from a variety of external clock sources (8, 16, 56, 64, 128, 256kHz and 1X, 2X, 4X, 8X T1 or E1) * Low Power dissipation: 170mW per channel (50% density). * 250mW per channel maximum power dissipation (100% density). * Driver failure monitor output (DMO) alerts of possible system or external component problems. * Single 3.3V supply operation (3V to 5V I/O tolerant). * Transmit outputs and receive inputs may be "High" impedance for protection or applications on a per channel basis. redundancy * Support for automatic protection switching. * 1:1 and 1+1 protection without relays. * Receive monitor mode handles 0 to 29dB resistive attenuation (flat loss) along with 0 to 6dB cable loss for both T1 and E1. * 304-Pin TBGA package * -40C to +85C Temperature Range * Supports gapped clocks for mapper/multiplexer applications. PRODUCT ORDERING INFORMATION PRODUCT NUMBER XRT83SL314IB PACKAGE TYPE 304 Lead TBGA OPERATING TEMPERATURE RANGE -40C to +85C 2 23 WRB_RWB TCLK_8 TPOS_10 TPOS_7 DGND_DRV RVDD_7 RTIP_7 RRING_7 RGND_7 RGND_6 RRING_6 RTIP_6 RVDD_6 MCLKOUT_T1 MCLKIN MCLKOUT_E1 MCLKE1xN TCLK_5 ICTB unnamed.12 22 A B C RGND_5 RRING_5 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A[10] CSB CSB4 unnamed.2 RESETB CSB1 CSB5 TPOS_8 TNEG_9 TNEG_10 TCLK_7 VDDPLL_21 RCLK_7 TVDD_7 TRING_7 TRING_6 TVDD_6 RCLK_6 MCLKT1xN TPOS_6 TCLK_3 TCLK_4 TPOS_4 INTB DGND_DRV unnamed.17 RGND_8 A[8] DVDD_DRV CSB3 ALE_AS TNEG_8 TCLK_9 TNEG_7 VDDPLL_22 RNEG_7 TTIP_7 DGND_6_7 TTIP_6 RNEG_6 GNDPLL_22 GNDPLL_21 TNEG_6 TNEG_3 TNEG_4 TPOS_5 DVDD_PRE TRING_5 PRELIMINARY RRING_8 TRING_8 unnamed.7 DVDD_PRE CSB2 RDB_DSB TPOS_9 TCLK_10 DGND_PRE RPOS_7 TGND_7 DVDD_6_7 TGND_6 RPOS_6 DVDD_DRV EIGHT_KHZ TCLK_6 TPOS_3 TNEG_5 TEST unnamed.13 TVDD_5 D RTIP_5 RTIP_8 RVDD_8 TVDD_8 A[9] unnamed.11 TTIP_5 RVDD_5 E RCLK_5 RVDD_4 RVDD_9 RCLK_8 TTIP_8 TGND_8 TGND_5 RNEG_5 F RNEG_4 RCLK_4 RTIP_4 PIN OUT OF THE XRT83SL314 RTIP_9 RCLK_9 RNEG_8 RPOS_8 RPOS_5 G RPOS_4 TTIP_4 TRING_4 RRING_4 RRING_9 TVDD_9 RNEG_9 RPOS_9 H TGND_4 TVDD_4 DVDD_3_4_5 RGND_4 RGND_9 TRING_9 TTIP_9 TGND_9 J AVDD_BIAS DVDD_DRV unnamed.14 unnamed.16 DVDD_8_9_10 unnamed.1 unnamed.3 unnamed.4 K DGND_PRE AGND_BIAS DGND_3_4_5 unnamed.10 DGND_8_9_10 unnamed.6 DGND_DRV DGND_PRE L TGND_3 TTIP_3 TRING_3 RGND_3 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 3 TGND_10 RGND_10 TRING_10 TTIP_10 Bottom View M RPOS_3 RNEG_3 TVDD_3 RRING_3 RRING_10 TVDD_10 RNEG_10 RPOS_10 N RPOS_2 RNEG_2 RCLK_3 RTIP_3 RTIP_10 RCLK_10 RNEG_11 RPOS_11 P TGND_2 TTIP_2 RCLK_2 RVDD_3 RVDD_10 RCLK_11 TTIP_11 TGND_11 R DGND_1_2 TVDD_2 RVDD_2 RTIP_2 RTIP_11 RVDD_11 TVDD_11 TRING_11 T TVDD_1 DGND_DRV TRING_2 RRING_2 RRING_11 DVDD_DRV DVDD_11_12 DGND_11_12 U TGND_1 TRING_1 DVDD_1_2 RGND_2 RGND_11 TRING_12 TVDD_12 TGND_12 V RPOS_1 TTIP_1 RGND_1 RRING_1 RRING_12 RGND_12 TTIP_12 RPOS_12 W TPOS_0 TNEG_1 D[3] DVDD_PRE DMO RNEG_1 RVDD_1 RTIP_1 RTIP_12 RCLK_12 RNEG_12 DVDD_PRE A[1] A[7] TCLK_12 TCLK_13 RXTSEL RPOS_13 TGND_13 DGND_13_0 TGND_0 RPOS_0 GNDPLL_12 Y RCLK_0 DGND_DRV TNEG_2 TPOS_1 D[4] D[7] RDY_DTACKB RCLK_1 unnamed.9 RVDD_12 unnamed.5 UPTS0 A[2] A[6] TPOS_12 TNEG_11 DVDD_DRV DVDD_UP RNEG_13 TTIP_13 DVDD_13_0 TTIP_0 RNEG_0 AA RVDD_0 DGND_PRE TNEG_0 TPOS_2 D[0] D[2] D[6] UPCLK RLOS DGND_DRV UPTS1 A[3] A[5] RXOFF TPOS_11 TPOS_13 VDDPLL_12 DGND_UP RCLK_13 TVDD_13 TRING_13 TRING_0 TVDD_0 AB RTIP_0 GNDPLL_11 TCLK_0 TCLK_2 TCLK_1 D[1] D[5] DVDD_DRV unnamed.0 REV. P1.0.5 UPTS2 A[0] A[4] TXOFF TNEG_12 TCLK_11 TNEG_13 VDDPLL_11 RVDD_13 RTIP_13 RRING_13 RGND_13 RGND_0 RRING_0 AC XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE OF CONTENTS GENERAL DESCRIPTION.............................................................................................................. 1 APPLICATIONS .......................................................................................................................................................... 1 FIGURE 1. BLOCK DIAGRAM OF THE XRT83SL314.................................................................................................................................. 1 FEATURES ..................................................................................................................................................................... 2 PRODUCT ORDERING INFORMATION ..................................................................................................2 PIN OUT OF THE XRT83SL314 ..................................................................................................... 3 TABLE OF CONTENTS ............................................................................................................I PIN DESCRIPTIONS....................................................................................................................... 3 MICROPROCESSOR ........................................................................................................................................................ 3 RECEIVER SECTION ....................................................................................................................................................... 4 TRANSMITTER SECTION.................................................................................................................................................. 7 CONTROL FUNCTION...................................................................................................................................................... 9 CLOCK SECTION ............................................................................................................................................................ 9 POWER AND GROUND .................................................................................................................................................. 10 NO CONNECTS ............................................................................................................................................................ 12 1.0 CLOCK SYNTHESIZER .......................................................................................................................13 TABLE 1: INPUT CLOCK SOURCE SELECT .............................................................................................................................................. 13 FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER................................................................................................... 14 1.1 ALL T1/E1 MODE ........................................................................................................................................... 14 2.0 RECEIVE PATH LINE INTERFACE .....................................................................................................14 FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH ............................................................................................................ 14 2.1 LINE TERMINATION (RTIP/RRING) .............................................................................................................. 15 2.1.1 CASE 1: INTERNAL TERMINATION.......................................................................................................................... 15 FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION .......................................................................................... 15 TABLE 2: SELECTING THE INTERNAL IMPEDANCE.................................................................................................................................... 15 2.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES..................... 16 FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR.............................................................................. 16 TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR.................................................................................................... 16 2.2 EQUALIZER CONTROL ................................................................................................................................. 17 FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER AND PEAK DETECTOR ................................................................................. 17 2.3 CABLE LOSS INDICATOR ............................................................................................................................. 17 FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE CABLE LOSS INDICATOR................................................................................................ 17 2.4 EQUALIZER ATTENUATION FLAG .............................................................................................................. 18 FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER ATTENUATION FLAG .................................................................................... 18 2.5 PEAK DETECTOR AND SLICER ................................................................................................................... 18 TABLE 4: SELECTING THE SLICER LEVEL FOR THE PEAK DETECTOR....................................................................................................... 18 2.6 CLOCK AND DATA RECOVERY ................................................................................................................... 19 FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK..................................................................................................... 19 FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK................................................................................................. 19 2.6.1 RECEIVE SENSITIVITY .............................................................................................................................................. 20 FIGURE 11. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY ............................................................................................ 20 TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG................................................................................................................. 20 2.6.2 INTERFERENCE MARGIN ......................................................................................................................................... 21 FIGURE 12. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN......................................................................................... 21 2.6.3 GENERAL ALARM DETECTION AND INTERRUPT GENERATION ........................................................................ 21 FIGURE 13. INTERRUPT GENERATION PROCESS BLOCK ......................................................................................................................... 21 2.6.3.1 RLOS (RECEIVER LOSS OF SIGNAL) ..................................................................................................................... 21 FIGURE 14. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1................................................................................................................ 22 2.6.3.2 EXLOS (EXTENDED LOSS OF SIGNAL) .................................................................................................................. 22 2.6.3.3 AIS (ALARM INDICATION SIGNAL) ......................................................................................................................... 22 TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 ............................................................................................. 22 2.6.3.4 NLCD (NETWORK LOOP CODE DETECTION) .......................................................................................................... 23 FIGURE 15. PROCESS BLOCK FOR AUTOMATIC LOOP CODE DETECTION ................................................................................................ 23 2.6.3.5 FLSD (FIFO LIMIT STATUS DETECTION) ............................................................................................................... 24 2.6.3.6 LCVD (LINE CODE VIOLATION DETECTION) ........................................................................................................... 24 2.7 RECEIVE JITTER ATTENUATOR .................................................................................................................. 24 2.8 HDB3/B8ZS DECODER .................................................................................................................................. 24 2.9 RPOS/RNEG/RCLK ........................................................................................................................................ 25 FIGURE 16. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ......................................................................................... 25 I XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.5 FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN ............................................................................................ 25 2.10 RXMUTE (RECEIVER LOS WITH DATA MUTING) ..................................................................................... 25 FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION................................................................................................... 25 3.0 TRANSMIT PATH LINE INTERFACE ................................................................................................. 26 FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH ......................................................................................................... 26 3.1 TCLK/TPOS/TNEG DIGITAL INPUTS ............................................................................................................ 26 FIGURE 20. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK...................................................................................................... 26 FIGURE 21. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK........................................................................................................ 26 3.2 HDB3/B8ZS ENCODER .................................................................................................................................. 27 TABLE 7: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG.................................................................................................................. 27 TABLE 8: EXAMPLES OF HDB3 ENCODING ............................................................................................................................................ 27 TABLE 9: EXAMPLES OF B8ZS ENCODING............................................................................................................................................. 27 3.3 TRANSMIT JITTER ATTENUATOR ............................................................................................................... 28 3.4 TAOS (TRANSMIT ALL ONES) ..................................................................................................................... 28 FIGURE 22. TAOS (TRANSMIT ALL ONES) ............................................................................................................................................ 28 3.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 28 TABLE 10: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS......................................................................................... 28 3.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29 FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 29 3.5.2 NETWORK LOOP UP CODE...................................................................................................................................... 29 FIGURE 24. NETWORK LOOP UP CODE GENERATION ............................................................................................................................ 29 3.5.3 NETWORK LOOP DOWN CODE ............................................................................................................................... 29 FIGURE 25. NETWORK LOOP DOWN CODE GENERATION ....................................................................................................................... 29 3.5.4 QRSS GENERATION.................................................................................................................................................. 30 3.6 TRANSMIT PULSE SHAPER AND FILTER ................................................................................................... 30 TABLE 11: RANDOM BIT SEQUENCE POLYNOMIALS................................................................................................................................ 30 3.6.1 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 31 3.6.2 ARBITRARY PULSE GENERATOR FOR T1 AND E1............................................................................................... 31 FIGURE 26. ARBITRARY PULSE SEGMENT ASSIGNMENT......................................................................................................................... 31 3.7 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31 TABLE 12: SHORT HAUL LINE BUILD OUT.............................................................................................................................................. 31 3.8 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 32 FIGURE 27. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 32 4.0 T1/E1 APPLICATIONS ........................................................................................................................ 33 4.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 33 4.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 33 FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 33 4.1.2 REMOTE LOOPBACK ................................................................................................................................................ 33 FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 33 4.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 34 FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 34 4.1.4 DUAL LOOPBACK ..................................................................................................................................................... 34 FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ............................................................................................................... 34 4.2 84-CHANNEL T1/E1 MULTIPLEXER/MAPPER APPLICATIONS ................................................................. 35 FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION ........................................................................................... 35 TABLE 13: CHIP SELECT ASSIGNMENTS ................................................................................................................................................ 35 4.3 LINE CARD REDUNDANCY .......................................................................................................................... 36 4.3.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 36 4.3.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 36 FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY................................................ 36 4.3.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 36 FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY.................................................. 37 4.3.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 37 4.3.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 38 FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ............................................................ 38 4.3.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 39 FIGURE 36. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY .............................................................. 39 4.4 POWER FAILURE PROTECTION .................................................................................................................. 40 4.5 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 40 4.6 NON-INTRUSIVE MONITORING .................................................................................................................... 40 FIGURE 37. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION ..................................................................... 40 4.7 XRT83SL314 JITTER CHARACTERISTICS .................................................................................................. 40 4.7.1 INTRINSIC JITTER...................................................................................................................................................... 40 II XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 4.7.2 JITTER TRANSFER CHARACTERISTICS................................................................................................................. 40 4.7.3 JITTER TOLERANCE AND WANDER ....................................................................................................................... 41 4.8 PULSE TEMPLATE ........................................................................................................................................ 41 5.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................42 TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 42 FIGURE 38. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 42 5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43 TABLE 15: XRT84L314 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES43 TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS........................................................................................................... 43 TABLE 17: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ................................................................................................. 44 5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45 FIGURE 39. INTEL P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................................. 46 TABLE 18: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................................. 46 5.3 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ....................................................... 47 FIGURE 40. MOTOROLA POWER PC P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS ....................... 48 TABLE 19: MOTOROLA POWER PC MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS ................................................................... 48 FIGURE 41. MOTOROLA 68K P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................. 49 TABLE 20: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................. 49 TABLE 21: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) .......................................................................................................... 50 TABLE 22: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION.......................................................................................................... 50 TABLE 23: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION............................................................................................................ 51 TABLE 24: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION........................................................................................................ 52 TABLE 25: EQUALIZER CONTROL AND TRANSMIT LINE BUILD OUT.......................................................................................................... 52 TABLE 26: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION........................................................................................................ 53 TABLE 27: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION........................................................................................................ 54 TABLE 28: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION........................................................................................................ 55 TABLE 29: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION........................................................................................................ 56 TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION........................................................................................................ 57 TABLE 31: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION........................................................................................................ 59 TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION........................................................................................................ 60 TABLE 33: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION........................................................................................................ 60 TABLE 34: MICROPROCESSOR REGISTER 0X09H BIT DESCRIPTION........................................................................................................ 61 TABLE 35: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION ....................................................................................................... 61 TABLE 36: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION ....................................................................................................... 61 TABLE 37: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION ....................................................................................................... 61 TABLE 38: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION ....................................................................................................... 62 TABLE 39: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION ....................................................................................................... 62 TABLE 40: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION........................................................................................................ 62 TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION ....................................................................................................... 63 TABLE 42: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION ....................................................................................................... 64 TABLE 43: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION ....................................................................................................... 64 TABLE 44: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION ....................................................................................................... 65 TABLE 45: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION ....................................................................................................... 66 TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION ....................................................................................................... 66 TABLE 47: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION ....................................................................................................... 67 TABLE 48: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTION ....................................................................................................... 68 TABLE 49: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION ....................................................................................................... 69 CLOCK SELECT REGISTER ....................................................................................................... 70 FIGURE 42. REGISTER 0XE9H SUB REGISTERS..................................................................................................................................... 70 TABLE 50: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION ....................................................................................................... 70 TABLE 51: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION ....................................................................................................... 72 TABLE 52: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION ....................................................................................................... 72 TABLE 53: E1 ARBITRARY SELECT........................................................................................................................................................ 73 TABLE 54: MICROPROCESSOR REGISTER 0XFFH BIT DESCRIPTION ....................................................................................................... 74 TABLE 55: ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................. 75 TABLE 56: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS........................................................................................... 75 TABLE 57: AC ELECTRICAL CHARACTERISTICS ...................................................................................................................................... 75 TABLE 58: POWER CONSUMPTION ........................................................................................................................................................ 76 TABLE 59: E1 RECEIVER ELECTRICAL CHARACTERISTICS ...................................................................................................................... 76 TABLE 60: T1 RECEIVER ELECTRICAL CHARACTERISTICS ...................................................................................................................... 77 TABLE 61: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS................................................................................................................. 78 TABLE 62: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS................................................................................................................. 78 ORDERING INFORMATION ......................................................................................................... 79 PACKAGE DIMENSIONS (DIE DOWN) ....................................................................................... 79 III XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.5 REVISION HISTORY ...................................................................................................................................................... 80 IV XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY PIN DESCRIPTIONS MICROPROCESSOR NAME CS PIN A22 TYPE I DESCRIPTION Chip Select Input Active low signal. This signal enables the microprocessor interface by pulling chip select "Low". The microprocessor interface is disabled when the chip select signal returns "High". Address Latch Enable Input (Transfer Start) See the Microprocessor section of this datasheet for a description. Write Strobe Input (Read/Write) See the Microprocessor section of this datasheet for a description. Read Strobe Input (Write Enable) See the Microprocessor section of this datasheet for a description. Ready Output (Transfer Acknowledge) See the Microprocessor section of this datasheet for a description. Interrupt Output Active low signal. This signal is asserted "Low" when a change in alarm status occurs. Once the status registers have been read, the interrupt pin will return "High". GIE (Global Interrupt Enable) must be set "High" in the appropriate global register to enable interrupt generation. ALE_TS C19 I WR_R/W A20 I RD_WE D18 I RDY_TA AA3 O INT B3 O NOTE: This pin is an open-drain output that requires an external 10K pull-up resistor. PCLK AB2 I Micro Processor Clock Input In a synchronous microprocessor interface, PCLK is used as the internal timing reference for programming the LIU. Address Bus Input ADDR[10:8] is used as a chip select decoder. The LIU has 5 chip select output pins for enabling up to 5 additional devices for accessing internal registers. The LIU has the option to select itself (master device), up to 5 additional devices, or all 6 devices simultaneously by setting the ADDR[10:8] pins specified below. ADDR[7:0] is a direct address bus for permitting access to the internal registers. ADDR[10:8] 000 = Master Device 001 = Chip Select Output 1 (Pin B21) 010 = Chip Select Output 2 (Pin D19) 011 = Chip Select Output 3 (Pin C20) 100 = Chip Select Output 4 (Pin A21) 101 = Chip Select Output 5 (Pin B20) 110 = Reserved 111 = All Chip Selects Active Including the Master Device ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 A23 E20 C22 Y18 AA19 AB20 AC21 AB21 AA20 Y19 AC22 I 3 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY MICROPROCESSOR NAME DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 PTS2 PTS1 PTS0 PIN AA4 AB3 AC3 AA5 Y6 AB4 AC4 AB5 AC23 AB22 AA21 TYPE I/O DESCRIPTION REV. P1.0.5 Bi-directional Data Bus DATA[7:0] is a bi-directional data bus used for read and write operations. I Microprocessor Type Select Input PTS[2:0] are used to select the microprocessor type interface. 000 = Intel 68HC11, 8051, 80C188 (Asynchronous) 001 = Motorola 68K (Asynchronous) 111 = Motorola MPC8260, MPC860 Power PC (Synchronous) Hardware Reset Input Active low signal. When this pin is pulled "Low" for more than 10S, the internal registers are set to their default state. See the register description for the default values. Reset B22 I NOTE: Internally pulled "High" with a 50K resistor. CS5 CS4 CS3 CS2 CS1 B20 A21 C20 D19 B21 O Chip Select Output The XRT83SL314 can be used to provide the necessary chip selects for up to 5 additional devices by using the 3 MSBs ADDR[10:8] from the 11-Bit address bus. The LIU allows up to 84-channel applications with only using one chip select. See the ADDR[10:0] definition in the pin description. RECEIVER SECTION NAME RxON PIN AB19 TYPE I DESCRIPTION Receive On/Off Input Upon power up, the receivers are powered off. Turning the receivers On or Off can be selected through the microprocessor interface by programming the appropriate channel register if the hardware pin is pulled "High". If the hardware pin is pulled "Low", all channels are automatically turned off. NOTE: Internally pulled "Low" with a 50K resistor. RxTSEL Y15 I Receive Termination Control Upon power up, the receivers are in "High" impedance. Switching to internal termination can be selected through the microprocessor interface by programming the appropriate channel register. However, to switch control to the hardware pin, RxTCNTL must be programmed to "1" in the appropriate global register. Once control has been granted to the hardware pin, it must be pulled "High" to switch to internal termination. NOTE: Internally pulled "Low" with a 50k resistor. 4 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY PIN AB1 TYPE O DESCRIPTION Receive Loss of Signal (Global Pin for All 14-Channels) When a receive loss of signal occurs for any one of the 14-channels according to ITU-T G.775, the RLOS pin will go "High" for a minimum of one RCLK cycle. RLOS will remain "High" until the loss of signal condition clears. See the Receive Loss of Signal section of this datasheet for more details. RECEIVER SECTION NAME RLOS NOTE: This pin is for redundancy applications to initiate an automatic switch to the backup card. For individual channel RLOS, see the register map. RCLK13 RCLK12 RCLK11 RCLK10 RCLK9 RCLK8 RCLK7 RCLK6 RCLK5 RCLK4 RCLK3 RCLK2 RCLK1 RCLK0 RPOS13 RPOS12 RPOS11 RPOS10 RPOS9 RPOS8 RPOS7 RPOS6 RPOS5 RPOS4 RPOS3 RPOS2 RPOS1 RPOS0 AB14 Y22 R22 P22 G22 F22 B14 B9 F2 G2 P2 R2 AA2 AA9 Y14 W20 P20 N20 H20 G20 D14 D10 G4 H4 N4 P4 W4 Y10 O Receive Clock Output RCLK is the recovered clock from the incoming data stream. If the incoming signal is absent or RxON is pulled "Low", RCLK maintains its timing by using an internal master clock as its reference. RPOS/RNEG data can be updated on either edge of RCLK selected by RCLKE in the appropriate global register. NOTE: RCLKE is a global setting that applies to all 14 channels. O RPOS/RDATA Output Receive digital output pin. In dual rail mode, this pin is the receive positive data output. In single rail mode, this pin is the receive non-return to zero (NRZ) data output. 5 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY RECEIVER SECTION NAME RNEG13 RNEG12 RNEG11 RNEG10 RNEG9 RNEG8 RNEG7 RNEG6 RNEG5 RNEG4 RNEG3 RNEG2 RNEG1 RNEG0 RTIP13 RTIP12 RTIP11 RTIP10 RTIP9 RTIP8 RTIP7 RTIP6 RTIP5 RTIP4 RTIP3 RTIP2 RTIP1 RTIP0 RRING13 RRING12 RRING11 RRING10 RRING9 RRING8 RRING7 RRING6 RRING5 RRING4 RRING3 RRING2 RRING1 RRING0 PIN AA14 Y21 P21 N21 H21 G21 C14 C10 F3 G3 N3 P3 Y3 AA10 AC14 Y23 T23 P23 G23 E23 A14 A9 E1 G1 P1 T1 Y1 AC9 AC13 W23 U23 N23 H23 D23 A13 A10 D1 H1 N1 U1 W1 AC10 TYPE O DESCRIPTION REV. P1.0.5 RNEG/LCV_OF Output In dual rail mode, this pin is the receive negative data output. In single rail mode, this pin is a Line Code Violation / Counter Overflow indicator. If LCV is selected by programming the appropriate global register and if a line code violation, a bi-polar violation, or excessive zeros occur, the LCV pin will pull "High" for a minimum of one RCLK cycle. LCV will remain "High" until there are no more violations. However, if OF is selected the LCV pin will pull "High" if the internal LCV counter is saturated. The LCV pin will remain "High" until the LCV counter is reset. I Receive Differential Tip Input RTIP is the positive differential input from the line interface. Along with the RRING signal, these pins should be coupled to a 1:1 transformer for proper operation. I Receive Differential Ring Input RRING is the negative differential input from the line interface. Along with the RTIP signal, these pins should be coupled to a 1:1 transformer for proper operation. 6 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TRANSMITTER SECTION NAME TxON PIN AC20 TYPE I DESCRIPTION Transmit On/Off Input Upon power up, the transmitters are powered off. Turning the transmitters On or Off is selected through the microprocessor interface by programming the appropriate channel register if this pin is pulled "High". If the TxON pin is pulled "Low", all 14 transmitters are powered off. NOTE: TxON is ideal for redundancy applications. See the Redundancy Applications Section of this datasheet for more details. Internally pulled "Low" with a 50K resistor. DMO Y4 O Digital Monitor Output (Global Pin for All 14-Channels) When no transmit output pulse is detected for more than 128 TCLK cycles on one of the 14-channels, the DMO pin will go "High" for a minimum of one TCLK cycle. DMO will remain "High" until the transmitter sends a valid pulse. NOTE: This pin is for redundancy applications to initiate an automatic switch to the backup card. For individual channel DMO, see the register map. TCLK13 TCLK12 TCLK11 TCLK10 TCLK9 TCLK8 TCLK7 TCLK6 TCLK5 TCLK4 TCLK3 TCLK2 TCLK1 TCLK0 TPOS13 TPOS12 TPOS11 TPOS10 TPOS9 TPOS8 TPOS7 TPOS6 TPOS5 TPOS4 TPOS3 TPOS2 TPOS1 TPOS0 Y16 Y17 AC18 D16 C17 A19 B16 D7 A3 B5 B6 AC6 AC5 AC7 AB17 AA18 AB18 A18 D17 B19 A17 B7 C4 B4 D6 AB6 AA6 Y8 I Transmit Clock Input TCLK is the input facility clock used to sample the incoming TPOS/TNEG data. If TCLK is absent, pulled "Low", or pulled "High", the transmitter outputs at TTIP/TRING can be selected to send an all ones or an all zero signal by programming TCLKCNL in the appropriate global register. TPOS/TNEG data can be sampled on either edge of TCLK selected by TCLKE in the appropriate global register. NOTE: TCLKE is a global setting that applies to all 14 channels. I TPOS/TDATA Input Transmit digital input pin. In dual rail mode, this pin is the transmit positive data input. In single rail mode, this pin is the transmit non-return to zero (NRZ) data input. NOTE: Internally pulled "Low" with a 50K resistor. 7 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TRANSMITTER SECTION NAME TNEG13 TNEG12 TNEG11 TNEG10 TNEG9 TNEG8 TNEG7 TNEG6 TNEG5 TNEG4 TNEG3 TNEG2 TNEG1 TNEG0 TTIP13 TTIP12 TTIP11 TTIP10 TTIP9 TTIP8 TTIP7 TTIP6 TTIP5 TTIP4 TTIP3 TTIP2 TTIP1 TTIP0 TRING13 TRING12 TRING11 TRING10 TRING9 TRING8 TRING7 TRING6 TRING5 TRING4 TRING3 TRING2 TRING1 TRING0 PIN AC17 AC19 AA17 B17 B18 C18 C16 C7 D5 C5 C6 AA7 Y7 AB7 AA13 W21 R21 M21 J21 F21 C13 C11 E3 H3 M3 R3 W3 AA11 AB12 V22 T20 M22 J22 D22 B12 B11 C2 H2 M2 U2 V3 AB11 TYPE I DESCRIPTION REV. P1.0.5 Transmit Negative Data Input In dual rail mode, this pin is the transmit negative data input. In single rail mode, this pin can be left unconnected. NOTE: Internally pulled "Low" with a 50K resistor. O Transmit Differential Tip Output TTIP is the positive differential output to the line interface. Along with the TRING signal, these pins should be coupled to a 1:2 step up transformer for proper operation. O Transmit Differential Ring Output TRING is the negative differential output to the line interface. Along with the TTIP signal, these pins should be coupled to a 1:2 step up transformer for proper operation. 8 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY CONTROL FUNCTION NAME TEST PIN D4 TYPE I DESCRIPTION Factory Test Mode For normal operation, the TEST pin should be tied to ground. NOTE: Internally pulled "Low" with a 50k resistor. ICT A2 I In Circuit Testing When this pin is tied "Low", all output pins are forced to "High" impedance for in circuit testing. NOTE: Internally pulled "High" with a 50K resistor. CLOCK SECTION NAME MCLKin PIN A6 TYPE I DESCRIPTION Master Clock Input The master clock input can accept a wide range of inputs that can be used to generate T1 or E1 clock rates on a per channel basis. See the register map for details. 8kHz Output Clock 2.048MHz Output Clock 2.048MHz, 4.096MHz, 8.192MHz, or 16.384MHz Output Clock See the register map for programming details. 1.544MHz Output Clock 1.544MHz, 3.088MHz, 6.176MHz, or 12.352MHz Output Clock See the register map for programming details. 8kHzOUT MCLKE1out MCLKE1Nout D8 A5 A4 O O O MCLKT1out MCLKT1Nout A7 B8 O O 9 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY POWER AND GROUND NAME TVDD13 TVDD12 TVDD11 TVDD10 TVDD9 TVDD8 TVDD7 TVDD6 TVDD5 TVDD4 TVDD3 TVDD2 TVDD1 TVDD0 RVDD13 RVDD12 RVDD11 RVDD10 RVDD9 RVDD8 RVDD7 RVDD6 RVDD5 RVDD4 RVDD3 RVDD2 RVDD1 RVDD0 DVDD DVDD DVDD DVDD DVDD DVDD PIN AB13 V21 T21 N22 H22 E21 B13 B10 D2 J3 N2 T3 U4 AB10 AC15 AA23 T22 R23 F23 E22 A15 A8 E2 F1 R1 T2 Y2 AB9 J2 V2 D12 AA12 U21 K23 TYPE PWR DESCRIPTION REV. P1.0.5 Transmit Analog Power Supply (3.3V 5%) TVDD can be shared with DVDD. However, it is recommended that TVDD be isolated from the analog power supply RVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1F capacitor. PWR Receive Analog Power Supply (3.3V 5%) RVDD should not be shared with other power supplies. It is recommended that RVDD be isolated from the digital power supply DVDD and the analog power supply TVDD. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through an external 0.1F capacitor. PWR Digital Power Supply (3.3V 5%) DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1F capacitor. 10 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY PIN C21 AC2 K3 D9 AA16 U22 C3 Y5 D20 Y20 AA15 K4 C15 B15 AB16 AC16 Y13 V20 R20 M20 J20 F20 D13 D11 F4 J4 M4 R4 V4 Y11 AC12 W22 V23 M23 J23 C23 A12 A11 C1 J1 M1 V1 W2 AC11 TYPE PWR DESCRIPTION Digital Power Supply (3.3V 5%) DVDD should be isolated from the analog power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Every two DVDD power supply pins should be bypassed to ground through at least one 0.1F capacitor. POWER AND GROUND NAME DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_DRV DVDD_PRE DVDD_PRE DVDD_PRE DVDD_PRE DVDD_UP AVDD_BIAS AVDD_PLL22 AVDD_PLL21 AVDD_PLL12 AVDD_PLL11 TGND13 TGND12 TGND11 TGND10 TGND9 TGND8 TGND7 TGND6 TGND5 TGND4 TGND3 TGND2 TGND1 TGND0 RGND13 RGND12 RGND11 RGND10 RGND9 RGND8 RGND7 RGND6 RGND5 RGND4 RGND3 RGND2 RGND1 RGND0 PWR Analog Power Supply (3.3V 5%) AVDD should be isolated from the digital power supplies. For best results, use an internal power plane for isolation. If an internal power plane is not available, a ferrite bead can be used. Each power supply pin should be bypassed to ground through at least one 0.1F capacitor. Transmit Analog Ground It's recommended that all ground pins of this device be tied together. GND GND Receive Analog Ground It's recommended that all ground pins of this device be tied together. 11 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY POWER AND GROUND NAME DGND DGND DGND DGND DGND DGND DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_DRV DGND_PRE DGND_PRE DGND_PRE DGND_PRE DGND_UP AGND_BIAS AGND_PLL22 AGND_PLL21 AGND_PLL12 AGND_PLL11 PIN L2 T4 C12 Y12 U20 L23 B2 U3 A16 AA8 L21 AB23 L4 D15 AB8 L20 AB15 L3 C9 C8 Y9 AC8 TYPE GND DESCRIPTION REV. P1.0.5 Digital Ground It's recommended that all ground pins of this device be tied together. GND Digital Ground It's recommended that all ground pins of this device be tied together. GND Analog Ground It's recommended that all ground pins of this device be tied together. NO CONNECTS NAME NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC PIN A1 B1 K1 L1 AA1 AC1 K2 D3 E4 K20 D21 K21 K22 L22 AA22 B23 TYPE NC DESCRIPTION No Connect This pin can be left floating or tied to ground. 12 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 1.0 CLOCK SYNTHESIZER In system design, fewer clocks on the network card could reduce noise and interference. Common clock references such as 8kHz are readily available to network designers. Network cards that support both T1 and E1 modes must be able to produce 1.544MHz and 2.048MHz transmission data. The XRT83SL314 has a built in clock synthesizer that requires only one input clock reference by programming CLKSEL[3:0] in the appropriate global register. A list of the input clock options is shown in Table 1. TABLE 1: INPUT CLOCK SOURCE SELECT CLKSEL[3:0] 0h (0000) 1h (0001) 2h (0010) 3h (0011) 4h (0100) 5h (0101) 6h (0110) 7h (0111) 8h (1000) 9h (1001) Ah (1010) Bh (1011) Ch (1100) Dh (1101) Eh (1110) Fh (1111) INPUT CLOCK REFERENCE 2.048 MHz 1.544MHz 8 kHz 16 kHz 56 kHz 64 kHz 128 kHz 256 kHz 4.096 MHz 3.088 MHz 8.192 MHz 6.176 MHz 16.384 MHz 12.352 MHz 2.048 MHz 1.544 MHz The single input clock reference is used to generate multiple timing references. The first objective of the clock synthesizer is to generate 1.544MHz and 2.048MHz for each of the 14 channels. This allows each channel to operate in either T1 or E1 mode independent from the other channels. The state of the equalizer control bits in the appropriate channel registers determine whether the LIU operates in T1 or E1 mode. The second objective is to generate additional output clock references for system use. The available output clock references are shown in Figure 2. 13 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY FIGURE 2. SIMPLIFIED BLOCK DIAGRAM OF THE CLOCK SYNTHESIZER REV. P1.0.5 Input Clock Clock Synthesizer Internal Reference 1.544MHz 2.048MHz 8kHzOUT MCLKT1out MCLKE1out MCLKE1Nout MCLKT1Nout Programmable Programmable 8kHz 1.544Mhz 2.048MHz 2.048/4.096/8.192/16.384 MHz 1.544/3.088/6.176/12.352MHz 1.1 ALL T1/E1 Mode To reduce system noise and power consumption, the XRT83SL314 offers an ALL T1/E1 mode. Since most line card designs are configured to operate in T1 or E1 only, the LIU can be selected to shut off the timing references for the mode not being used by programming the appropriate global register. By default the ALL T1/E1 mode is enabled (ALLT1/E1 bit = "0"). If the LIU is configured for T1, all E1 clock references and the 8kHz reference are shut off internally to the chip. This reduces the amount of internal clocks switching within the LIU, hence reducing noise and power consumption. In E1 mode, the T1 clock references are internally shut off, however the 8kHz reference is available. To disable this feature, the ALLT1/E1 bit must be set to a "1" in the appropriate global register. 2.0 RECEIVE PATH LINE INTERFACE The receive path of the XRT83SL314 LIU consists of 14 independent T1/E1/J1 receivers. The following section describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified block diagram of the receive path is shown in Figure 3. FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE PATH RCLK RPOS RNEG HDB3/B8ZS Decoder Rx Jitter Attenuator Clock & Data Recovery Peak Detector & Slicer Rx Equalizer RTIP RRING Rx Equalizer Control 14 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY CASE 1: Internal Termination 2.1 2.1.1 Line Termination (RTIP/RRING) The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The receive termination (along with the transmit termination) impedance is selected by programming TERSEL[1:0] to match the line impedance. Selecting the internal impedance is shown in Table 2. TABLE 2: SELECTING THE INTERNAL IMPEDANCE TERSEL[1:0] 0h (00) 1h (01) 2h (10) 3h (11) RECEIVE TERMINATION 100 110 75 120 The XRT83SL314 has the ability to switch the internal termination to "High" impedance by programming RxTSEL in the appropriate channel register. For internal termination, set RxTSEL to "1". By default, RxTSEL is set to "0" ("High" impedance). For redundancy applications, a dedicated hardware pin (RxTSEL) is also available to control the receive termination for all channels simultaneously. This hardware pin takes priority over the register setting if RxTCNTL is set to "1" in the appropriate global register. If RxTCNTL is set to "0", the state of this pin is ignored. See Figure 4 for a typical connection diagram using the internal termination. FIGURE 4. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SL314 LIU Receiver Input RTIP 1:1 Line Interface T1/E1/J1 RRING One Bill of Materials Internal Impedance 15 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 2.1.2 CASE 2: Internal Termination With One External Fixed Resistor for All Modes REV. P1.0.5 Along with the internal termination, a high precision external fixed resistor can be used to optimize the return loss. This external resistor can be used for all modes of operation ensuring one bill of materials. There are three resistor values that can be used by setting the RxRES[1:0] bits in the appropriate channel register. Selecting the value for the external fixed resistor is shown in Table 3. TABLE 3: SELECTING THE VALUE OF THE EXTERNAL FIXED RESISTOR RXRES[1:0] 0h (00) 1h (01) 2h (10) 3h (11) EXTERNAL FIXED RESISTOR None 240 210 150 By default, RxRES[1:0] is set to "None" for no external fixed resistor. If an external fixed resistor is used, the XRT83SL314 uses the parallel combination of the external fixed resistor and the internal termination as the input impedance. See Figure 5 for a typical connection diagram using the external fixed resistor. NOTE: Without the external resistor, the XRT83SL314 meets all return loss specifications. This mode was created to add flexibility for optimizing return loss by using a high precision external resistor. FIGURE 5. TYPICAL CONNECTION DIAGRAM USING ONE EXTERNAL FIXED RESISTOR XRT83SL314 LIU Receiver Input RTIP R 1:1 Line Interface T1/E1/J1 RRING R=240, 210, or 150 Internal Impedance 16 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 2.2 Equalizer Control The main objective of the equalizer is to amplify an input attenuated signal to a pre-determined amplitude that is acceptable to the peak detector circuit. Using feedback from the peak detector, the equalizer will gain the input up to the maximum value specified by the equalizer control bits, in the appropriate channel register, normalizing the signal. Once the signal has reached the pre-determined amplitude, the signal is then processed within the peak detector and slicer circuit. A simplified block diagram of the equalizer and peak detector is shown in Figure 6. FIGURE 6. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER AND PEAK DETECTOR Peak Detector & Slicer RTIP Rx Equalizer RRING Rx Equalizer Control 2.3 Cable Loss Indicator The ability to monitor the cable loss attenuation of the receiver inputs is a valuable feature. The XRT83SL314 contains a per channel, read only register for cable loss indication. CLOS[5:0] is a 6-Bit binary word that reports the value of cable loss in 1dB steps. An example of -15dB cable loss attenuation is shown in Figure 7. FIGURE 7. SIMPLIFIED BLOCK DIAGRAM OF THE CABLE LOSS INDICATOR -15dB Attenuated Signal -15dB of Cable Loss Equalizer and Peak Detector XRT83SL314 Read Only CLOS[5:0] = 0x0Fh (15dec = 0Fhex) 17 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 2.4 Equalizer Attenuation Flag REV. P1.0.5 The ability to detect the amount of cable loss on the receiver inputs is enhanced by having the ability to generate an interrupt by programming a pre-determined value for cable loss into the EQFLAG[5:0] global register. This is particularly useful in applications where it is necessary for the LIU to generate an interrupt for a cable loss which is lower than the declaration of the RLOS feature (see the RLOS section in this datasheet). If the contents of the EQFLAG[5:0] register bits are equal to or less than the contents in the cable loss indicator bits CLOS[5:0] for a given channel, an interrupt will be generated (if enabled in the appropriate channel register and GIE is to "1"). Using the same example in Figure 7, a simplified block diagram of the equalizer flag is shown in Figure 8. FIGURE 8. SIMPLIFIED BLOCK DIAGRAM OF THE EQUALIZER ATTENUATION FLAG Receiver Inputs RTIP/RRING -15dB of Cable Loss Equalizer and Peak Detector XRT83SL314 Read Only CLOS[5:0] = 0x0Fh If (CLOS = EQFLAG) Generate an Interrupt EQFLAG[5:0] = 0x0Fh Programmable 2.5 Peak Detector and Slicer The peak detector provides feedback to the equalizer control circuit until the amplitude of the incoming signal is at an appropriate level. Once this level is obtained, the slicer identifies the incoming signal as a "1" and passes the raw data to the clock and data recovery circuit. The slicer threshold is selected by programming SL[1:0] in the appropriate global register. Selecting the slicer level is shown in Table 4. TABLE 4: SELECTING THE SLICER LEVEL FOR THE PEAK DETECTOR SL[1:0] 0h (00) 1h (01) 2h (10) 3h (11) SLICER LEVEL 50% 45% 55% 68% 18 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 2.6 Clock and Data Recovery The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the incoming data stream and outputs a clock that's in phase with the incoming signal. This allows for multichannel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register. Figure 9 is a timing diagram of the receive data updated on the rising edge of RCLK. Figure 10 is a timing diagram of the receive data updated on the falling edge of RCLK. The timing specifications are shown in Table 5. FIGURE 9. RECEIVE DATA UPDATED ON THE RISING EDGE OF RCLK R CLKR R CLKF R DY R C LK RPOS or RNEG ROH FIGURE 10. RECEIVE DATA UPDATED ON THE FALLING EDGE OF RCLK RDY RCLKF RCLKR RCLK RPOS or RNEG ROH 19 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 5: TIMING SPECIFICATIONS FOR RCLK/RPOS/RNEG PARAMETER RCLK Duty Cycle Receive Data Setup Time Receive Data Hold Time RCLK to Data Delay RCLK Rise Time (10% to 90%) with 25pF Loading RCLK Fall Time (90% to 10%) with 25pF Loading SYMBOL RCDU RSU RHO RDY RCLKR RCLKF MIN 45 150 150 TYP 50 MAX 55 40 40 40 REV. P1.0.5 UNITS % ns ns ns ns ns NOTE: VDD=3.3V 5%, TA=25C, Unless Otherwise Specified 2.6.1 Receive Sensitivity To meet short haul requirements, the XRT83SL314 can accept T1/E1/J1 signals that have been attenuated by 12dB of flat loss in E1 mode or by 655 feet of cable loss along with 6dB of flat loss in T1 mode. However, the XRT83SL314 can tolerate cable loss and flat loss beyond the industry specifications. The receive sensitivity in the short haul mode is approximately 4,000 feet without experiencing bit errors, LOF, pattern synchronization, etc. Although data integrity is maintained, the RLOS function (if enabled) will report an RLOS condition according to the receiver loss of signal section in this datasheet. The test configuration for measuring the receive sensitivity is shown in Figure 11. FIGURE 11. TEST CONFIGURATION FOR MEASURING RECEIVE SENSITIVITY W&G ANT20 Tx Cable Loss Network Analyzer Rx Rx Flat Loss Tx XRT83SL314 14-Channel Long Haul LIU External Loopback E1 = PRBS 215 - 1 T1 = PRBS 223 - 1 20 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY Interference Margin 2.6.2 The interference margin for the XRT83SL314 will be added when the first revision of silicon arrives. The test configuration for measuring the interference margin is shown in Figure 12. FIGURE 12. TEST CONFIGURATION FOR MEASURING INTERFERENCE MARGIN E1 = 1,024kHz T1 = 772kHz Sinewave Generator E1 = PRBS 215 - 1 T1 = PRBS 223 - 1 W&G ANT20 Network Analyzer Tx Cable Loss Rx Tx XRT83SL314 14-Channel LIU Rx External Loopback Flat Loss 2.6.3 General Alarm Detection and Interrupt Generation The receive path detects EQFLAG, RLOS, AIS, QRPD, NCLD, and FLS. These alarms can be individually masked to prevent the alarm from triggering an interrupt. To enable interrupt generation, the Global Interrupt Enable (GIE) bit must be set "High" in the appropriate global register. Any time a change in status occurs (it the alarms are enabled), the interrupt pin will pull "Low" to indicate an alarm has occurred. Once the status registers have been read, the INT pin will return "High". The status registers are Reset Upon Read (RUR). The interrupts are categorized in a hierarchical process block. Figure 13 is a simplified block diagram of the interrupt generation process. FIGURE 13. INTERRUPT GENERATION PROCESS BLOCK Global Interrupt Enable (GIE="1") Global Channel Interrupt Status (Indicates Which Channel(s) Experienced a Change in Status) Individual Alarm Status Change (Indicates Which Alarm Experienced a Change) Individual Alarm Indication (Indicates the Alarm Condition Active/Inactive) NOTE: The interrupt pin is an open-drain output that requires a 10k external pull-up resistor. 2.6.3.1 RLOS (Receiver Loss of Signal) 21 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.5 In T1 mode, RLOS is declared if an incoming signal has no transitions over a period of 175 +/-75 contiguous pulse intervals. However, the XRT83SL314 LIU has a built in analog RLOS so that the user can be notified when the amplitude of the incoming signal has been attenuated -9dB below the equalizer gain setting. For example: In T1 or E1 short haul mode, the equalizer gain setting is 15dB. Once the input reaches an amplitude of -24dB below nominal, the LIU will declare RLOS. The RLOS circuitry clears when the input reaches +3dB relative to where it was declared. This +3dB value is a pre-determined hysteresis so that transients will not cause the RLOS to clear. In E1 mode, RLOS is declared if an incoming signal has no transitions for N consecutive pulse intervals, where 10N255. According to G.775, no transitions in E1 mode is defined between -9dB and -35dB below nominal. Figure 14 is a simplified block diagram of the analog RLOS function. Table 6 summarizes the analog RLOS values for the different equalizer gain settings. FIGURE 14. ANALOG RECEIVE LOS OF SIGNAL FOR T1/E1/J1 Normalized up to EQC[4:0] Setting -9dB +3dB Declare LOS Clear LOS Declare LOS +3dB -9dB Clear LOS Normalized up to EQC[4:0] Setting TABLE 6: ANALOG RLOS DECLARE/CLEAR (TYPICAL VALUES) FOR T1/E1 GAIN SETTING 15dB (Short Haul Mode) 29dB (Monitoring Gain Mode) DECLARE -24dB -38dB CLEAR -21dB -35dB NOTE: For programming the equalizer gain setting on a per channel basis, see the microprocessor register map for details. 2.6.3.2 EXLOS (Extended Loss of Signal) By enabling the extended loss of signal by programming the appropriate channel register, the digital RLOS is extended to count 4,096 consecutive zeros before declaring RLOS in T1 and E1 mode. By default, EXLOS is disabled and RLOS operates in normal mode. 2.6.3.3 AIS (Alarm Indication Signal) The XRT83SL314 adheres to the ITU-T G.775 specification for an all ones pattern. The alarm indication signal is set to "1" if an all ones pattern (at least 99.9% ones density) is present for T, where T is 3ms to 75ms in T1 mode. AIS will clear when the ones density is not met within the same time period T. In E1 mode, the AIS is set to "1" if the incoming signal has 2 or less zeros in a 512-bit window. AIS will clear when the incoming signal has 3 or more zeros in the 512-bit window. 22 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY NLCD (Network Loop Code Detection) 2.6.3.4 The Network Loop Code Detection can be programmed to detect a Loop-Up, Loop-Down, or Automatic Loop Code. If the network loop code detection is programmed for Loop-Up, the NLCD will be set "High" if a repeating pattern of "00001" occurs for more than 5 seconds. If the network loop code detection is programmed for Loop-Down, the NLCD will be set "High" if a repeating pattern of "001" occurs for more than 5 seconds. If the network loop code detection is programmed for automatic loop code, the LIU is configured to detect a Loop-Up code. If a Loop-Up code is detected for more than 5 seconds, the XRT83SL314 will automatically program the channel into a remote loopback mode. The LIU will remain in remote loopback even if the Loop-Up code disappears. The channel will continue in remote loop back until a Loop-Down code is detected for more than 5 seconds (or, if the automatic loop code is disabled) and then automatically return to normal operation with no loop back. The process of the automatic loop code detection is shown in Figure 15. FIGURE 15. PROCESS BLOCK FOR AUTOMATIC LOOP CODE DETECTION No Loop-Up Code for 5 sec? Yes Automatic Remote Loopback No Loop-Down Code for 5 sec? Yes Disable Remote Loopback 23 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 2.6.3.5 FLSD (FIFO Limit Status Detection) REV. P1.0.5 The purpose of the FIFO limit status is to indicate when the Read and Write FIFO pointers are within a predetermined range (over-flow or under-flow indication). The FLSD is set to "1" if the FIFO Read and Write Pointers are within 3-Bits. 2.6.3.6 LCVD (Line Code Violation Detection) The LIU contains 14 independent, 16-bit LCV counters. When the counters reach full-scale, they remain saturated at FFFFh until they are reset globally or on a per channel basis. For performance monitoring, the counters can be updated globally or on a per channel basis to place the contents of the counters into holding registers. The LIU uses an indirect address bus to access a counter for a given channel. Once the contents of the counters have been placed in holding registers, they can be individually read out from register 0xE8h 8-bits at a time according to the BYTEsel bit in the appropriate global register. By default, the LSB is in register 0xE8h until the BYTEsel is pulled "High" where upon the MSB will be placed in the register for read back. Once both bytes have been read, the next channel may be selected for read back. By default, the LVC/OFD will be set to a "1" if the receiver is currently detecting line code violations or excessive zeros for HDB3 (E1 mode) or B8ZS (T1 mode). In AMI mode, the LCVD will be set to a "1" if the receiver is currently detecting bipolar violations or excessive zeros. However, if the LIU is configured to monitor the 16-bit LCV counter by programming the appropriate global register, the LCV/OFD will be set to a "1" if the counter saturates. 2.7 Receive Jitter Attenuator The receive path has a dedicated jitter attenuator that reduces phase and frequency jitter in the recovered clock. The jitter attenuator uses a data FIFO (First In First Out) with a programmable depth of 32-bit or 64-bit. If the LIU is used for line synchronization (loop timing systems), the JA should be enabled. When the Read and Write pointers of the FIFO are within 2-Bits of over-flowing or under-flowing, the bandwidth of the jitter attenuator is widened to track the short term input jitter, thereby avoiding data corruption. When this condition occurs, the jitter attenuator will not attenuate input jitter until the Read/Write pointer's position is outside the 2Bit window. In T1 mode, the bandwidth of the JA is always set to 3Hz. In E1 mode, the bandwidth is programmable to either 10Hz or 1.5Hz (1.5Hz automatically selects the 64-Bit FIFO depth). The JA has a clock delay equal to 1/2 of the FIFO bit depth. NOTE: If the LIU is used in a multiplexer/mapper application where stuffing bits are typically removed, the transmit path has a dedicated jitter attenuator to smooth out the gapped clock. See the Transmit Section of this datasheet. 2.8 HDB3/B8ZS Decoder In single rail mode, RPOS can decode AMI or HDB3/B8ZS signals. For E1 mode, HDB3 is defined as any block of 4 successive zeros replaced with OOOV or BOOV, so that two successive V pulses are of opposite polarity to prevent a DC component. In T1 mode, 8 successive zeros are replaced with OOOVBOVB. If the HDB3/B8ZS decoder is selected, the receive path removes the V and B pulses so that the original data is output to RPOS. 24 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 2.9 RPOS/RNEG/RCLK The digital output data can be programmed to either single rail or dual rail formats. Figure 16 is a timing diagram of a repeating "0011" pattern in single-rail mode. Figure 17 is a timing diagram of the same fixed pattern in dual rail mode. FIGURE 16. SINGLE RAIL MODE WITH A FIXED REPEATING "0011" PATTERN 0 RCLK 0 1 1 0 RPOS FIGURE 17. DUAL RAIL MODE WITH A FIXED REPEATING "0011" PATTERN 0 RCLK 0 1 1 0 RPOS RNEG 2.10 RxMUTE (Receiver LOS with Data Muting) The receive muting function can be selected by setting RxMUTE to "1" in the appropriate global register. If selected, any channel that experiences an RLOS condition will automatically pull RPOS and RNEG "Low" to prevent data chattering. If RLOS does not occur, the RxMUTE will remain inactive until an RLOS on a given channel occurs. The default setting for RxMUTE is "0" which is disabled. A simplified block diagram of the RxMUTE function is shown in Figure 18. FIGURE 18. SIMPLIFIED BLOCK DIAGRAM OF THE RXMUTE FUNCTION RPOS RNEG RxMUTE RLOS 25 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 3.0 TRANSMIT PATH LINE INTERFACE REV. P1.0.5 The transmit path of the XRT83SL314 LIU consists of 14 independent T1/E1/J1 transmitters. The following section describes the complete transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the transmit path is shown in Figure 19. FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT PATH TCLK TPOS TNEG HDB3/B8ZS Encoder Tx Jitter Attenuator Timing Control Tx Pulse Shaper & Pattern Gen TTIP Line Driver TRING 3.1 TCLK/TPOS/TNEG Digital Inputs In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG has no function and can be left unconnected. The XRT83SL314 can be programmed to sample the inputs on either edge of TCLK. By default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKE to "1" in the appropriate global register. Figure 20 is a timing diagram of the transmit input data sampled on the falling edge of TCLK. Figure 21 is a timing diagram of the transmit input data sampled on the rising edge of TCLK. The timing specifications are shown in Table 7. FIGURE 20. TRANSMIT DATA SAMPLED ON FALLING EDGE OF TCLK TCLKR TCLKF TCLK TPOS or TNEG TSU THO FIGURE 21. TRANSMIT DATA SAMPLED ON RISING EDGE OF TCLK TCLKF TCLKR TCLK TPOS or TNEG TSU THO 26 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 7: TIMING SPECIFICATIONS FOR TCLK/TPOS/TNEG PARAMETER SYMBOL TCDU TSU THO TCLKR TCLKF MIN 30 50 30 TYP 50 MAX 70 40 40 UNITS % ns ns ns ns TCLK Duty Cycle Transmit Data Setup Time Transmit Data Hold Time TCLK Rise Time (10% to 90%) TCLK Fall Time (90% to 10%) NOTE: VDD=3.3V 5%, TA=25C, Unless Otherwise Specified 3.2 HDB3/B8ZS Encoder In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3/B8ZS data. In E1 mode and HDB3 encoding selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V, where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An example of HDB3 encoding is shown in Table 8. In T1 mode and B8ZS encoding selected, an input data sequence with eight or more consecutive zeros will be replaced using the B8ZS encoding rule. An example with Bipolar with 8 Zero Substitution is shown in Table 9. TABLE 8: EXAMPLES OF HDB3 ENCODING NUMBER OF PULSES BEFORE NEXT 4 ZEROS Input HDB3 (Case 1) HDB3 (Case 2) Odd Even 0000 000V B00V TABLE 9: EXAMPLES OF B8ZS ENCODING CASE 1 Input B8ZS AMI Output + Case 2 Input B8ZS AMI Output 00000000 000VB0VB 000-+0+PRECEDING PULSE + NEXT 8 BITS 00000000 000VB0VB 000+-0-+ 27 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 3.3 Transmit Jitter Attenuator REV. P1.0.5 The XRT83SL314 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. As the higher data rates are de-multiplexed down to T1 or E1 data, stuffing bits are typically removed which can leave gaps in the incoming data stream. The transmit path has a dedicated jitter attenuator with a 32-Bit or 64-Bit FIFO that is used to smooth the gapped clock into a steady T1 or E1 output. The maximum gap width of the 14-Channel LIU is shown in Table 10. TABLE 10: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS FIFO DEPTH 32-Bit 64-Bit MAXIMUM GAP WIDTH 20 UI 50 UI NOTE: If the LIU is used in a loop timing system, the receive path has a dedicated jitter attenuator. See the Receive Section of this datasheet. 3.4 TAOS (Transmit All Ones) The XRT83SL314 has the ability to transmit all ones on a per channel basis by programming the appropriate channel register. This function takes priority over the digital data present on the TPOS/TNEG inputs. For example: If a fixed "0011" pattern is present on TPOS in single rail mode and TAOS is enabled, the transmitter will output all ones. In addition, if digital or dual loopback is selected, the data on the RPOS output will be equal to the data on the TPOS input. Figure 22 is a diagram showing the all ones signal at TTIP and TRING. FIGURE 22. TAOS (TRANSMIT ALL ONES) 1 TAOS 1 1 3.5 Transmit Diagnostic Features In addition to TAOS, the XRT83SL314 offers multiple diagnostic features for analyzing network integrity such as ATAOS, Network Loop Code generation, and QRSS on a per channel basis by programming the appropriate registers. These diagnostic features take priority over the digital data present on TPOS/TNEG inputs. The transmitters will send the diagnostic code to the line and will be maintained in the digital loopback if selected. When the LIU is responsible for sending diagnostic patterns, the LIU is automatically placed in the single rail mode. 28 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY ATAOS (Automatic Transmit All Ones) 3.5.1 If ATAOS is selected by programming the appropriate global register, an AMI all ones signal will be transmitted for each channel that experiences an RLOS condition. If RLOS does not occur, the ATAOS will remain inactive until an RLOS on a given channel occurs. A simplified block diagram of the ATAOS function is shown in Figure 23. FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION Tx TTIP TRING TAOS ATAOS RLOS 3.5.2 Network Loop Up Code By setting the LIU to generate a NLUC, the transmitters will send out a repeating "00001" pattern. The output waveform is shown in Figure 24. FIGURE 24. NETWORK LOOP UP CODE GENERATION 1 Network Loop-Up Code 0 0 0 0 1 0 0 0 0 1 3.5.3 Network Loop Down Code By setting the LIU to generate a NLDC, the transmitters will send out a repeating "001" pattern. The output waveform is shown in Figure 25. FIGURE 25. NETWORK LOOP DOWN CODE GENERATION 1 Network Loop-Down Code 0 0 1 0 0 1 0 0 1 0 29 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 3.5.4 QRSS Generation REV. P1.0.5 The XRT83SL314 can transmit a QRSS random sequence to a remote location from TTIP/TRING. The polynomial is shown in Table 11. TABLE 11: RANDOM BIT SEQUENCE POLYNOMIALS RANDOM PATTERN QRSS T1 220 - 1 E1 215 - 1 3.6 Transmit Pulse Shaper and Filter If TCLK is not present, pulled "Low", or pulled "High" the transmitter outputs at TTIP/TRING will automatically send an all ones or an all zero signal to the line by programming the appropriate global register. By default, the transmitters will send all zeros. To send all ones, the TCLKCNL bit must be set "High". 30 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY T1 Short Haul Line Build Out (LBO) 3.6.1 The short haul transmitter output pulses are generated using a 7-Bit internal DAC (6-Bit plus the MSB sign bit). The line build out can be set to interface to five different ranges of cable attenuation by programming the appropriate channel register. The pulse shape is divided into eight discrete time segments which are set to fixed values to comply with the pulse template. To program the eight segments individually to optimize a special line build out, see the arbitrary pulse section of this datasheet. The short haul LBO settings are shown in Table 12. TABLE 12: SHORT HAUL LINE BUILD OUT LBO SETTING EQC[4:0] 08h (01000) 09h (01001) 0Ah (01010) 0Bh (01011) 0Ch (01100) RANGE OF CABLE ATTENUATION 0 - 133 Feet 133 - 266 Feet 266 - 399 Feet 399 - 533 Feet 533 - 655 Feet 3.6.2 Arbitrary Pulse Generator For T1 and E1 The arbitrary pulse generator divides the pulse into eight individual segments. Each segment is set by a 7-Bit binary word by programming the appropriate channel register. This allows the system designer to set the overshoot, amplitude, and undershoot for a unique line build out. The MSB (bit 7) is a sign-bit. If the sign-bit is set to "0", the segment will move in a positive direction relative to a flat line (zero) condition. If this sign-bit is set to "1", the segment will move in a negative direction relative to a flat line condition. The resolution of the DAC is typically 60mV per LSB. Thus, writing 7-bit = 1111111 will clamp the output at either voltage rail corresponding to a maximum amplitude. A pulse with numbered segments is shown in Figure 26. FIGURE 26. ARBITRARY PULSE SEGMENT ASSIGNMENT 1 2 3 Segment 1 2 3 4 5 6 7 8 Register 0xn8 0xn9 0xna 0xnb 0xnc 0xnd 0xne 0xnf 4 8 7 6 5 NOTE: By default, the arbitrary segments are programmed to 0x00h. The transmitter outputs will result in an all zero pattern to the line interface. 3.7 DMO (Digital Monitor Output) The driver monitor circuit is used to detect transmit driver failures by monitoring the activities at TTIP/TRING outputs. Driver failure may be caused by a short circuit in the primary transformer or system problems at the transmit inputs. If the transmitter of a channel has no output for more than 128 clock cycles, DMO goes "High" until a valid transmit pulse is detected. If the DMO interrupt is enabled, the change in status of DMO will cause 31 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 3.8 Line Termination (TTIP/TRING) REV. P1.0.5 the interrupt pin to go "Low". Once the status register is read, the interrupt pin will return "High" and the status register will be reset (RUR). The output stage of the transmit path generates standard return-to-zero (RZ) signals to the line interface for T1/E1/J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The transmitter outputs only require one DC blocking capacitor of 0.68F. For redundancy applications (or simply to tri-state the transmitters), set TxTSEL to a "1" in the appropriate channel register. A typical transmit interface is shown in Figure 27. FIGURE 27. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION XRT83SL314 LIU TTIP Transmitter Output C=0.68uF TRING Line Interface T1/E1/J1 1:2 One Bill of Materials Internal Impedance 32 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 4.0 T1/E1 APPLICATIONS This applications section describes common T1/E1 system considerations along with references to application notes available for reference where applicable. 4.1 Loopback Diagnostics The XRT83SL314 supports several loopback modes for diagnostic testing. The following section describes the local analog loopback, remote loopback, digital loopback, and dual loopback modes. 4.1.1 Local Analog Loopback With local analog loopback activated, the transmit output data at TTIP/TRING is internally looped back to the analog inputs at RTIP/RRING. External inputs at RTIP/RRING are ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of local analog loopback is shown in Figure 28. FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK NLC/PRBS/QRSS TCLK TPOS TNEG Timing Control TAOS Encoder JA Tx TTIP TRING RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING NOTE: The transmit diagnostic features such as TAOS, NLC generation, and QRSS take priority over the transmit input data at TCLK/TPOS/TNEG. 4.1.2 Remote Loopback With remote loopback activated, the receive input data at RTIP/RRING is internally looped back to the transmit output data at TTIP/TRING. The remote loopback includes the Receive JA (if enabled). The transmit input data at TCLK/TPOS/TNEG are ignored while valid receive output data continues to be sent to the system. A simplified block diagram of remote loopback is shown in Figure 29. FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK NLC/PRBS/QRSS TCLK TPOS TNEG Timing Control TAOS TTIP TRING Encoder JA Tx RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING 33 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 4.1.3 Digital Loopback REV. P1.0.5 With digital loopback activated, the transmit input data at TCLK/TPOS/TNEG is looped back to the receive output data at RCLK/RPOS/RNEG. The digital loopback mode includes the Transmit JA (if enabled). The receive input data at RTIP/RRING is ignored while valid transmit output data continues to be sent to the line. A simplified block diagram of digital loopback is shown in Figure 30. FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK NLC/PRBS/QRSS TCLK TPOS TNEG Timing Control TAOS Encoder JA Tx TTIP TRING RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING 4.1.4 Dual Loopback With dual loopback activated, the remote loopback is combined with the digital loopback. A simplified block diagram of dual loopback is shown in Figure 31. FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK NLC/PRBS/QRSS TCLK TPOS TNEG Timing Control TAOS Encoder JA Tx TTIP TRING RCLK RPOS RNEG Decoder JA Data and Clock Recovery Rx RTIP RRING 34 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 4.2 84-Channel T1/E1 Multiplexer/Mapper Applications The XRT83SL314 has the capability of providing the necessary chip selects for multiple 14-channel LIU devices. The LIU is responsible for selecting itself, up to 5 additional LIU devices, or all 6 devices simultaneously for permitting access to internal registers. The state of the chip select output pins is determined by a chip select decoder controlled by the 3 MSBs of the address bus ADDR[10:8]. Only one LIU (Master) requires the ADDR[10:8]. The other 5 LIU devices use the 8 LSBs for the direct address bus ADDR[7:0]. Figure 32 is a simplified block diagram of connecting six 14-channel LIU devices for 84-channel applications. Selection of the chip select outputs using ADDR[10:8] is shown in Table 13. FIGURE 32. SIMPLIFIED BLOCK DIAGRAM OF AN 84-CHANNEL APPLICATION Master CS[4:0] CS Slave CS Slave CS Slave CS Slave CS Slave XRT83SL314 1 XRT83SL314 2 XRT83SL314 3 XRT83SL314 4 XRT83SL314 5 XRT83SL314 6 Data [7:0] Address A[7:0] Chip Address A[10:8] TABLE 13: CHIP SELECT ASSIGNMENTS ADDR[10:8] 0h (000) 1h (001) 2h (010) 3h (011) 4h (100) 5h (101) 6h (110) 7h (111) ACTIVE CHIP SELECT Current Device (Master) Chip 1 Chip 2 Chip 3 Chip 4 Chip 5 Reserved All Devices Active 35 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 4.3 Line Card Redundancy REV. P1.0.5 Telecommunication system design requires signal integrity and reliability. When a T1/E1 primary line card has a failure, it must be swapped with a backup line card while maintaining connectivity to a backplane without losing data. System designers can achieve this by implementing common redundancy schemes with the XRT83SL314 LIU. EXAR offers features that are tailored to redundancy applications while reducing the number of components and providing system designers with solid reference designs. RLOS and DMO If an RLOS or DMO condition occurs, the XRT83SL314 reports the alarm to the individual status registers on a per channel basis. However, for redundancy applications, an RLOS or DMO alarm can be used to initiate an automatic switch to the back up card. For this application, two global pins RLOS and DMO are used to indicate that one of the 14-channels has an RLOS or DMO condition. Typical Redundancy Schemes * 1:1 One backup card for every primary card (Facility Protection) * 1+1 One backup card for every primary card (Line Protection) * *N+1 One backup card for N primary cards 4.3.1 1:1 and 1+1 Redundancy Without Relays The 1:1 facility protection and 1+1 line protection have one backup card for every primary card. When using 1:1 or 1+1 redundancy, the backup card has its transmitters tri-stated and its receivers in high impedance. This eliminates the need for external relays and provides one bill of materials for all interface modes of operation. For 1+1 line protection, the receiver inputs on the backup card have the ability to monitor the line for bit errors while in high impedance. The transmit and receive sections of the LIU device are described separately. 4.3.2 Transmit Interface with 1:1 and 1+1 Redundancy The transmitters on the backup card should be tri-stated. Select the appropriate impedance for the desired mode of operation, T1/E1/J1. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 33. for a simplified block diagram of the transmit section for a 1:1 and 1+1 redundancy. FIGURE 33. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SL314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Backup Card XRT83SL314 1:2 Tx 0.68uF Internal Impedence 4.3.3 Receive Interface with 1:1 and 1+1 Redundancy The receivers on the backup card should be programmed for "High" impedance. Since there is no external resistor in the circuit, the receivers on the backup card will not load down the line interface. This key design feature eliminates the need for relays and provides one bill of materials for all interface modes of operation. Select the impedance for the desired mode of operation, T1/E1/J1. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 34. for a simplified block diagram of the receive section for a 1:1 redundancy scheme. 36 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY Backplane Interface Primary Card XRT83SL314 1:1 Rx T1/E1 Line Internal Impedence Backup Card XRT83SL314 1:1 Rx "High" Impedence 4.3.4 N+1 Redundancy Using External Relays N+1 redundancy has one backup card for N primary cards. Due to impedance mismatch and signal contention, external relays are necessary when using this redundancy scheme. The relays create complete isolation between the primary cards and the backup card. This allows all transmitters and receivers on the primary cards to be configured in internal impedance, providing one bill of materials for all interface modes of operation. The transmit and receive sections of the LIU device are described separately. 37 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 4.3.5 Transmit Interface with N+1 Redundancy REV. P1.0.5 For N+1 redundancy, the transmitters on all cards should be programmed for internal impedance. The transmitters on the backup card do not have to be tri-stated. To swap the primary card, close the desired relays, and tri-state the transmitters on the failed primary card. A 0.68uF capacitor is used in series with TTIP for blocking DC bias. See Figure 35 for a simplified block diagram of the transmit section for an N+1 redundancy scheme. FIGURE 35. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY Backplane Interface Line Interface Card Primary Card XRT83SL314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Primary Card XRT83SL314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Primary Card XRT83SL314 1:2 Tx 0.68uF T1/E1 Line Internal Impedence Backup Card XRT83SL314 Tx Internal Impedence 0.68uF 38 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY Receive Interface with N+1 Redundancy 4.3.6 For N+1 redundancy, the receivers on the primary cards should be programmed for internal impedance. The receivers on the backup card should be programmed for "High" impedance mode. To swap the primary card, set the backup card to internal impedance, then the primary card to "High" impedance. See Figure 36 for a simplified block diagram of the receive section for a N+1 redundancy scheme. FIGURE 36. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY Backplane Interface Line Interface Card Primary Card XRT83SL314 1:1 Rx T1/E1 Line Internal Impedence Primary Card XRT83SL314 1:1 Rx T1/E1 Line Internal Impedence Primary Card XRT83SL314 1:1 Rx T1/E1 Line Internal Impedence Backup Card XRT83SL314 Rx "High" Impedence 39 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY 4.4 Power Failure Protection REV. P1.0.5 For 1:1 or 1+1 line card redundancy in T1/E1 applications, power failure could cause a line card to change the characteristics of the line impedance, causing a degradation in system performance. The XRT83SL314 was designed to ensure reliability during power failures. The LIU has patented high impedance circuits that allow the receiver inputs and the transmitter outputs to be in "High" impedance when the LIU experiences a power failure or when the LIU is powered off. NOTE: For power failure protection, a transformer must be used to couple to the line interface. See the TAN-56 application note for more details. 4.5 Overvoltage and Overcurrent Protection Physical layer devices such as LIUs that interface to telecommunications lines are exposed to overvoltage transients posed by environmental threats. An Overvoltage transient is a pulse of energy concentrated over a small period of time, usually under a few milliseconds. These pulses are random and exceed the operating conditions of CMOS transceiver ICs. Electronic equipment connecting to data lines are susceptible to many forms of overvoltage transients such as lightning, AC power faults and electrostatic discharge (ESD). There are three important standards when designing a telecommunications system to withstand overvoltage transients. * UL1950 and FCC Part 68 * Telcordia (Bellcore) GR-1089 * ITU-T K.20, K.21 and K.41 NOTE: For a reference design and performance, see the TAN-54 application note for more details. 4.6 Non-Intrusive Monitoring In non-intrusive monitoring applications, the transmitters are shut off by setting TxON "Low". The receivers must be actively receiving data without interfering with the line impedance. The XRT83SL314's internal termination ensures that the line termination meets T1/E1 specifications for 75, 100 or 120 while monitoring the data stream. System integrity is maintained by placing the non-intrusive receiver in "High" impedance, equivalent to that of a 1+1 redundancy application. A simplified block diagram of non-intrusive monitoring is shown in Figure 37. FIGURE 37. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION XRT83SL314 Line Card Transceiver Data Traffic Node XRT83SL314 Non-Intrusive Receiver 4.7 XRT83SL314 Jitter Characteristics There are three important jitter requirements for T1/E1 physical layer devices. Intrinsic Jitter, Jitter Transfer Characteristics, and Jitter Tolerance and Wander. 4.7.1 Intrinsic Jitter The XRT83SL314 exceeds the intrinsic jitter requirements for T1/E1 specifications. The intrinsic jitter of the 14-Channel LIU is typically 0.015 UIp-p 4.7.2 Jitter Transfer Characteristics 40 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY Jitter Tolerance and Wander To be Added When First Revision of Silicon Arrives. 4.7.3 4.8 To be Added When First Revision of Silicon Arrives. Pulse Template To be Added When First Revision of Silicon Arrives. 41 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.5 5.0 MICROPROCESSOR INTERFACE BLOCK The Microprocessor Interface section supports communication between the local microprocessor (P) and the LIU. The XRT83SL314 supports an Intel asynchronous interface, Motorola 68K asynchronous, and a Motorola Power PC interface. The microprocessor interface is selected by the state of the PTS[2:0] input pins. Selecting the microprocessor interface is shown in Table 14. TABLE 14: SELECTING THE MICROPROCESSOR INTERFACE MODE PTS[2:0] 0h (000) 1h (001) 7h (111) MICROPROCESSOR MODE Intel 68HC11, 8051, 80C188 (Asynchronous) Motorola 68K (Asynchronous) Motorola MPC8260, MPC860 Power PC (Synchronous) The XRT83SL314 uses multipurpose pins to configure the device appropriately. The local P configures the LIU by writing data into specific addressable, on-chip Read/Write registers. The microprocessor interface provides the signals which are required for a general purpose microprocessor to read or write data into these registers. The microprocessor interface also supports polled and interrupt driven environments. A simplified block diagram of the microprocessor is shown in Figure 38. FIGURE 38. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK CS WR_R/W RD_WE ALE ADDR[10:0] DATA[7:0] Pclk PType [2:0] Reset RDY_TA INT CS5 CS4 CS3 CS2 CS1 Microprocessor Interface 42 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS The LIU may be configured into different operating modes and have its performance monitored by software through a standard microprocessor using data, address and control signals. These interface signals are described below in Table 15, Table 16, and Table 17. The microprocessor interface can be configured to operate in Intel mode or Motorola mode. When the microprocessor interface is operating in Intel mode, some of the control signals function in a manner required by the Intel 80xx family of microprocessors. Likewise, when the microprocessor interface is operating in Motorola mode, then these control signals function in a manner as required by the Motorola Power PC family of microprocessors. (For using a Motorola 68K asynchronous processor, see Figure 41 and Table 20) Table 15 lists and describes those microprocessor interface signals whose role is constant across the two modes. Table 16 describes the role of some of these signals when the microprocessor interface is operating in the Intel mode. Likewise, Table 17 describes the role of these signals when the microprocessor interface is operating in the Motorola Power PC mode. TABLE 15: XRT84L314 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES PIN NAME TYPE I DESCRIPTION Microprocessor Interface Mode Select Input pins These three pins are used to specify the microprocessor interface mode. The relationship between the state of these three input pins, and the corresponding microprocessor mode is presented in Table 14. Bi-Directional Data Bus for register "Read" or "Write" Operations. Three-Bit Address Bus Inputs The 3 MSBs of the address bits are used as a chip select decoder. The state of these 3 pins enable the Chip Selects for additional LIU devices. NOTE: See the 84-Channel Application Section of this datasheet. Eight-Bit Address Bus Inputs The XRT83SL314 LIU microprocessor interface uses a direct address bus. This address bus is provided to permit the user to select an on-chip register for Read/Write access. Chip Select Input This active low signal selects the microprocessor interface of the XRT83SL314 LIU and enables Read/Write operations with the on-chip register locations. PTS[2:0] DATA[7:0] ADDR[10:8] I/O I ADDR[7:0] I CS I TABLE 16: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS XRT83SL314 INTEL PIN NAME EQUIVALENT PIN ALE_TS ALE TYPE I DESCRIPTION Address-Latch Enable: This active high signal is used to latch the contents on the address bus ADDR[7:0]. The contents of the address bus are latched into the ADDR[7:0] inputs on the falling edge of ALE. Read Signal: This active low input functions as the read signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a read operation has been requested and begins the process of the read cycle. Write Signal: This active low input functions as the write signal from the local P. When this pin is pulled "Low" (if CS is "Low") the LIU is informed that a write operation has been requested and begins the process of the write cycle. Ready Output: This active low signal is provided by the LIU device. It indicates that the current read or write cycle is complete, and the LIU is waiting for the next command. RD_WE RD I WR_R/W WR I RDY_TA RDY O 43 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 17: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS XRT83SL314 MOTOROLA PIN NAME EQUIVALENT PIN ALE_TS TS TYPE I DESCRIPTION REV. P1.0.5 Transfer Start: This active high signal is used to latch the contents on the address bus ADDR[7:0]. The contents of the address bus are latched into the ADDR[7:0] inputs on the falling edge of TS. Read/Write: This input pin from the local P is used to inform the LIU whether a Read or Write operation has been requested. When this pin is pulled "High", WE will initiate a read operation. When this pin is pulled "Low", WE will initiate a write operation. Write Enable: This active low input functions as the read or write signal from the local P dependent on the state of R/W. When WE is pulled "Low" (If CS WR_R/W R/W I RD_WE WE I is "Low") the LIU begins the read or write operation. No Pin PCLK OE CLKOUT TA I I O Output Enable: This signal is not necessary for the XRT83SL314 to interface to the MPC8260 or MPC860 Power PCs. Synchronous Processor Clock: This signal is used as the timing reference for the Power PC synchronous mode. Transfer Acknowledge: This active low signal is provided by the LIU device. It indicates that the current read or write cycle is complete, and the LIU is waiting for the next command. RDY_TA 44 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) If the LIU is interfaced to an Intel type P, then it should be configured to operate in the Intel mode. Intel type Read and Write operations are described below. Intel Mode Read Cycle Whenever an Intel-type P wishes to read the contents of a register, it should do the following. 1. Place the address of the target register on the address bus input pins ADDR[10:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the P and the LIU microprocessor interface block. 3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microprocessor interface block of the LIU. 4. The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address bus into its internal circuitry. At this point, the address of the register has now been selected. 5. Next, the P should indicate that this current bus cycle is a Read operation by toggling the RD input pin "Low". This action also enables the bi-directional data bus output drivers of the LIU. 6. After the P toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this in order to inform the P that the data is available to be read by the P, and that it is ready for the next command. 7. After the P detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the RD input pin "High". NOTE: ALE can be tied "High" if this signal is not available. The Intel Mode Write Cycle Whenever an Intel type P wishes to write a byte or word of data into a register within the LIU, it should do the following. 1. Place the address of the target register on the address bus input pins ADDR[10:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the P and the LIU microprocessor interface block. 3. Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microprocessor interface block of the LIU. 4. The P should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address bus into its internal circuitry. At this point, the address of the register has now been selected. 5. The P should then place the byte or word that it intends to write into the target register, on the bi-directional data bus DATA[7:0]. 6. Next, the P should indicate that this current bus cycle is a Write operation by toggling the WR input pin "Low". This action also enables the bi-directional data bus input drivers of the LIU. 7. After the P toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this in order to inform the P that the data has been written into the internal register location, and that it is ready for the next command. NOTE: ALE can be tied "High" if this signal is not available. The Intel Read and Write timing diagram is shown in Figure 39. The timing specifications are shown in Table 18. 45 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY FIGURE 39. INTEL P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS READ OPERATION ALE = 1 t0 Valid Address t0 Valid Address REV. P1.0.5 WRITE OPERATION ADDR[10:0] CS DATA[7:0] t1 RD Valid Data for Readback Data Available to Write Into the LIU t3 WR t2 t4 RDY TABLE 18: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS SYMBOL t0 t1 t2 NA t3 t4 NA PARAMETER Valid Address to CS Falling Edge CS Falling Edge to RD Assert RD Assert to RDY Assert RD Pulse Width (t2) CS Falling Edge to WR Assert WR Assert to RDY Assert WR Pulse Width (t4) MIN 0 30 150 30 150 MAX 150 150 ns ns ns ns ns ns ns UNITS 46 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY 5.3 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) If the LIU is interfaced to a Motorola type P, it should be configured to operate in the Motorola mode. Motorola type programmed I/O Read and Write operations are described below. Motorola Mode Read Cycle Whenever a Motorola type P wishes to read the contents of a register, it should do the following. 1. Place the address of the target register on the address bus input pins ADDR[10:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the P and the LIU microprocessor interface block. 3. The P should then toggle the TS pin "Low". This step causes the LIU to latch the contents of the address bus into its internal circuitry. At this point, the address of the register has now been selected. 4. Next, the P should indicate that this current bus cycle is a Read operation by pulling the R/W input pin "High". 5. Toggle the WE input pin "Low". This action enables the bi-directional data bus output drivers of the LIU. 6. After the P toggles the WE signal "Low", the LIU will toggle the TA output pin "Low". The LIU does this in order to inform the P that the data is available to be read by the P, and that it is ready for the next command. 7. After the P detects the TA signal and has read the data, it can terminate the Read Cycle by toggling the WE input pin "High". Motorola Mode Write Cycle Whenever a motorola type P wishes to write a byte or word of data into a register within the LIU, it should do the following. 1. Place the address of the target register on the address bus input pins ADDR[10:0]. 2. While the P is placing this address value on the address bus, the address decoding circuitry should assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the P and the LIU microprocessor interface block. 3. The P should then toggle the TS pin "Low". This step causes the LIU to latch the contents of the address bus into its internal circuitry. At this point, the address of the register has now been selected. 4. Next, the P should indicate that this current bus cycle is a Write operation by pulling the R/W input pin "Low". 5. Toggle the WE input pin "Low". This action enables the bi-directional data bus output drivers of the LIU. 6. After the P toggles the WE signal "Low", the LIU will toggle the TA output pin "Low". The LIU does this in order to inform the P that the data has been written into the internal register location, and that it is ready for the next command. 7. After the P detects the TA signal and has read the data, it can terminate the Read Cycle by toggling the WE input pin "High". The Motorola Read and Write timing diagram is shown in Figure 40. The timing specifications are shown in Table 19. 47 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY REV. P1.0.5 FIGURE 40. MOTOROLA POWER PC P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS READ OPERATION WRITE OPERATION TS tdc uPCLK t0 ADDR[10:0] t3 CS tcp t0 Valid Address t3 Valid Address DATA[7:0] t1 WE Valid Data for Readback t1 Data Available to Write Into the LIU R/W t2 t2 TA TABLE 19: MOTOROLA POWER PC MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS SYMBOL t0 t1 t2 NA t3 tdc tcp PARAMETER Valid Address to CS Falling Edge CS Falling Edge to WE Assert WE Assert to TA Assert WE Pulse Width (t2) CS Falling Edge to TS Falling Edge PCLK Duty Cycle PCLK Clock Period MIN 0 0 150 0 40 20 MAX 150 60 ns ns ns ns ns % ns UNITS 48 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY FIGURE 41. MOTOROLA 68K P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS MOTOROLA ASYCHRONOUS MODE READ OPERATION WRITE OPERATION ALE_TS t0 Valid Address t3 t0 Valid Address t3 ADDR[10:0] CS DATA[7:0] t1 RD_WE Valid Data for Readback t1 Data Available to Write Into the LIU WR_R/W t2 t2 RDY_DTACK TABLE 20: MOTOROLA 68K MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS SYMBOL t0 t1 t2 NA t3 PARAMETER Valid Address to CS Falling Edge CS Falling Edge to DS (Pin RD_WE) Assert DS Assert to DTACK Assert DS Pulse Width (t2) CS Falling Edge to AS (Pin ALE_TS) Falling Edge MIN 0 30 150 0 MAX 150 ns ns ns ns ns UNITS 49 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 21: MICROPROCESSOR REGISTER ADDRESS (ADDR[7:0]) REGISTER NUMBER 0 - 15 16 - 31 32 - 47 48 - 63 64 - 79 80 - 95 96 - 111 112 - 127 128 - 143 144 - 159 160 - 175 176 - 191 192 - 207 208 - 223 224 - 227 228 - 243 244 245 - 253 254 255 ADDRESS (HEX) 0x00 - 0x0F 0x10 - 0x1F 0x20 - 0x2F 0x30 - 0x3F 0x40 - 0x4F 0x50 - 0x5F 0x60 - 0x6F 0x70 - 0x7F 0x80 - 0x8F 0x90 - 0x9F 0xA0 - 0xAF 0xB0 - 0xBF 0xC0 - 0xCF 0xD0 - 0xDF 0xE0 - 0xEB 0xEC - 0xF3 0xF4 0xF5 - 0xFD 0xFE 0xFF Channel 0 Control Registers Channel 1 Control Registers Channel 2 Control Registers Channel 3 Control Registers Channel 4 Control Registers Channel 5 Control Registers Channel 6 Control Registers Channel 7 Control Registers Channel 8 Control Registers Channel 9 Control Registers Channel 10 Control Registers Channel 11 Control Registers Channel 12 Control Registers Channel 13 Control Registers Global Control Registers Applied to All 14 Channels R/W Registers Reserved for Testing E1 Arbitrary Select R/W Registers Reserved for Testing Device "ID" Device "Revision ID" FUNCTION REV. P1.0.5 TABLE 22: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 Channel 0 Control Registers (0x00 - 0x0F) 0 1 2 3 4 5 6 0x00 0x01 0x02 0x03 0x04 0x05 0x06 R/W R/W R/W R/W R/W RO RUR Reserved RxTSEL INVQRSS NLCDE1 EQFLAGE EQFLAG EQFLAGS Reserved TxTSEL TxTEST2 NLCDE0 DMOIE DMO DMOIS RxON TERSEL1 TxTEST1 CODES FLSIE FLS FLSIS EQC4 TERSEL0 TxTEST0 RxRES1 LCVI/OFE LCV/OF LCV/OFIS EQC3 RxJASEL TxON RxRES0 NLCDIE NLCD NLCDIS EQC2 TxJASEL LOOP2 INSBPV AISDIE AIS AISIS EQC1 JABW LOOP1 INSBER RLOSIE RLOS RLOSIS EQC0 FIFOS LOOP0 Reserved QRPDIE QRPD QRPDIS 50 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 22: MICROPROCESSOR REGISTER CHANNEL DESCRIPTION D7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved REG 7 8 9 10 11 12 13 14 15 ADDR TYPE 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F RO R/W R/W R/W R/W R/W R/W R/W R/W D6 FLSDET 1SEG6 2SEG6 3SEG6 4SEG6 5SEG6 6SEG6 7SEG6 8SEG6 D5 CLOS5 1SEG5 2SEG5 3SEG5 4SEG5 5SEG5 6SEG5 7SEG5 8SEG5 D4 CLOS4 1SEG4 2SEG4 3SEG4 4SEG4 5SEG4 6SEG4 7SEG4 8SEG4 D3 CLOS3 1SEG3 2SEG3 3SEG3 4SEG3 5SEG3 6SEG3 7SEG3 8SEG3 D2 CLOS2 1SEG2 2SEG2 3SEG2 4SEG2 5SEG2 6SEG2 7SEG2 8SEG2 D1 CLOS1 1SEG1 2SEG1 3SEG1 4SEG1 5SEG1 6SEG1 7SEG1 8SEG1 D0 CLOS0 1SEG0 2SEG0 3SEG0 4SEG0 5SEG0 6SEG0 7SEG0 8SEG0 Channel (1 - 13) Control Registers (0xN0 - 0xNF) See Channel 0 TABLE 23: MICROPROCESSOR REGISTER GLOBAL DESCRIPTION REG ADDR TYPE D7 D6 D5 D4 D3 D2 D1 D0 Global Control Registers for All 14 Channels 224 225 226 227 228 229 230 231 232 233 234 235 244 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xF4 R/W R/W R/W R/W R/W R/W R/W R/W RO R/W RUR RUR R/W SR/DR Reserved Reserved Reserved MCLKT1out1 LCV/OFLW Reserved Reserved LCVCNT7 Reserved GCHIS7 Reserved Reserved ATAOS Reserved RxTCNTL Reserved MCLKT1out0 CNTRDEN Reserved Reserved LCVCNT6 Reserved GCHIS6 Reserved Reserved RCLKE GAUGE1 EQFLAG5 Reserved MCLKE1out1 Reserved Reserved Reserved LCVCNT5 ALLT1E1 GCHIS5 GCHIS13 Reserved TCLKE GAUGE0 EQFLAG4 Reserved MCLKE1out0 Reserved allRST Reserved LCVCNT4 TCLKCNL GCHIS4 GCHIS12 Reserved DATAP Reserved EQFLAG3 SL1 Reserved LCVCH3 allUPDATE Reserved LCVCNT3 CLKSEL3 GCHIS3 GCHIS11 Reserved Reserved RxMUTE EQFLAG2 SL0 Reserved LCVCH2 BYTEsel Reserved LCVCNT2 CLKSEL2 GCHIS2 GCHIS10 Reserved GIE EXLOS EQFLAG1 EQG1 Reserved LCVCH1 chUPDATE Reserved LCVCNT1 CLKSEL1 GCHIS1 GCHIS9 Reserved SRESET ICT EQFLAG0 EQG0 Reserved LCVCH0 chRST Reserved LCVCNT0 CLKSEL0 GCHIS0 GCHIS8 E1arben R/W Registers Reserved for Testing (0xEC - 0xFD), Excluding 0xF4h 254 255 0xFE 0xFF RO RO Device "ID" Device "Revision ID" 51 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 24: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION CHANNEL 0-13 (0X00H-0XD0H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) D7 D6 D5 Reserved Reserved RxON This Register Bit is Not Used. This Register Bit is Not Used. Receiver ON/OFF Upon power up, the receiver is powered OFF. RxON is used to turn the receiver ON or OFF if the hardware pin RxON is pulled "High". If the hardware pin is pulled "Low", all receivers are turned off. 0 = Receiver is Powered Off 1 = Receiver is Powered On Equalizer Control Bits The equalizer control bits are shown in Table 25 below. R/W 0 D4 D3 D2 D1 D0 EQC4 EQC3 EQC2 EQC1 EQC0 R/W 0 0 0 0 0 TABLE 25: EQUALIZER CONTROL AND TRANSMIT LINE BUILD OUT EQC[4:0] 0x08h 0x09h 0x0Ah 0x0Bh 0x0Ch 0x0Dh 0x0Eh 0x0Fh 0x10h 0x11h 0x12h 0x13h 0x1Ch 0x1Dh T1/E1 MODE/RECEIVE SENSITIVITY T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Short Haul/15dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB T1 Gain Mode/29dB E1 Short Haul/15dB E1 Short Haul/15dB TRANSMIT LBO 0 to 133 feet (0.6dB) 133 to 266 feet (1.2dB) 266 to 399 feet (1.8dB) 399 to 533 feet (2.4dB) 533 to 655 feet (3.0dB) Arbitrary Pulse 0 to 133 feet (0.6dB) 133 to 266 feet (1.2dB) 266 to 399 feet (1.8dB) 399 to 533 feet (2.4dB) 533 to 655 feet (3.0dB) Arbitrary Pulse ITU G.703 ITU G.703 CABLE 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 100 TP 75 Coax 120 TP CODING B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS B8ZS HDB3 HDB3 52 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 25: EQUALIZER CONTROL AND TRANSMIT LINE BUILD OUT T1/E1 MODE/RECEIVE SENSITIVITY E1 Gain Mode/29dB E1 Gain Mode/29dB TRANSMIT LBO ITU G.703 ITU G.703 CABLE 75 Coax 120 TP CODING HDB3 HDB3 EQC[4:0] 0x1Eh 0x1Fh TABLE 26: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION CHANNEL 0-13 (0X01H-0XD1H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 RxTSEL Receive Termination Select Upon power up, the receiver is in "High" impedance. RxTSEL is used to switch between the internal termination and "High" impedance. 0 = "High" Impedance 1 = Internal Termination Transmit Termination Select Upon power up, the transmitter is in "High" impedance. TxTSEL is used to switch between the internal termination and "High" impedance. 0 = "High" Impedance 1 = Internal Termination Receive Line Impedance Select TERSEL[1:0] are used to select the line impedance for T1/J1/E1. 00 = 100 01 = 110 10 = 75 11 = 120 Receive Jitter Attenuator Select RxJASEL is used to enable the receiver jitter attenuator. default, RxJASEL is disabled. 0 = Disabled 1 = Enabled R/W D6 TxTSEL R/W 0 D5 D4 TERSEL1 TERSEL0 R/W 0 0 D3 RxJASEL R/W By 0 D2 TxJASEL Transmit Jitter Attenuator Select TxJASEL is used to enable the transmitter jitter attenuator. By default, TxJASEL is disabled. 0 = Disabled 1 = Enabled R/W 0 53 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 26: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION CHANNEL 0-13 (0X01H-0XD1H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 D1 JABW Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz) The jitter bandwidth is a global setting that is applied to both the receiver and transmitter jitter attenuator. 0 = 10Hz 1 = 1.5Hz FIFO Depth Select The FIFO depth select is used to configure the part for a 32-bit or 64-bit FIFO (within the jitter attenuator blocks). The delay of the FIFO is equal to 1/2 the FIFO depth. This is a global setting that is applied to both the receiver and transmitter FIFO. 0 = 32-Bit 1 = 64-Bit R/W D0 FIFOS R/W 0 TABLE 27: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION CHANNEL 0-13 (0X02H-0XD2H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 INVQRSS QRSS inversion INVQRSS is used to invert the transmit QRSS pattern set by the TxTEST[2:0] bits. By default, INVQRSS is disabled and the QRSS will be transmitted with normal polarity. 0 = Disabled 1 = Enabled Test Code Pattern TxTEST[2:0] are used to select a diagnostic test pattern to the line (transmit outputs). 0XX = No Pattern 100 = Tx QRSS 101 = Tx TAOS 110 = Tx TLUC 111 = Tx TLDC R/W D6 D5 D4 TxTEST2 TxTEST1 TxTEST0 R/W 0 0 0 54 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 27: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION CHANNEL 0-13 (0X02H-0XD2H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D3 TxOn Transmit ON/OFF Upon power up, the transmitters are powered off. This bit is used to turn the transmitter for this channel On or Off if the TxON pin is pulled "High". If the TxON pin is pulled "Low", all 14 transmitters are powered off. 0 = Transmitter is Powered OFF 1 = Transmitter is Powered ON Loopback Diagnostic Select LOOP[2:0] are used to select the loopback mode. 0XX = No Loopback 100 = Dual Loopback 101 = Analog Loopback 110 = Remote Loopback 111 = Digital Loopback R/W D2 D1 D0 LOOP2 LOOP1 LOOP0 R/W 0 0 0 TABLE 28: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION CHANNEL 0-13 (0X03H-0XD3H) Register Type Default Value (HW reset) 0 0 BIT NAME FUNCTION D7 D6 NLCDE1 NLCDE0 Network Loop Code Detection Enable NLCDE[1:0] are used to select the loop code detection. 00 = Disabled 01 = Detect Loop Up Code 10 = Detect Loop Down Code 11 = Automatic Loop Code Detection Encoding/Decoding Select (Single Rail Mode Only) 0 = HDB3 (E1), B8ZS (T1) 1 = AMI Coding Receive External Fixed Resistor RxRES[1:0] are used to select the value for a high precision external resistor to improve return loss. 00 = None 01 = 240 10 = 210 11 = 150 R/W D5 CODES R/W 0 D4 D3 RxRES1 RxRES0 R/W 0 0 55 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 28: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION CHANNEL 0-13 (0X03H-0XD3H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 D2 INSBPV Insert Bipolar Violation When this bit transitions from a "0" to a "1", a bipolar violation will be inserted in the transmitted QRSS/PRBS pattern. The state of this bit will be sampled on the rising edge of TCLK. To ensure proper operation, it is recommended to write a "0" to this bit before writing a "1". Insert Bit Error When this bit transitions from a "0" to a "1", a bit error will be inserted in the transmitted QRSS/PRBS pattern. The state of this bit will be sampled on the rising edge of TCLK. To ensure proper operation, it is recommended to write a "0" to this bit before writing a "1". This Register Bit is Not Used. R/W D1 INSBER R/W 0 D0 Reserved TABLE 29: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION CHANNEL 0-13 (0X04H-0XD4H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 EQFLAGE Equalizer Attenuation Flag Enable 0 = Masks the EQFLAG function 1 = Enables Interrupt Generation DMOIE Digital Monitor Output Interrupt Enable 0 = Masks the DMO function 1 = Enables Interrupt Generation FIFO Limit Status Interrupt Enable 0 = Masks the FLS function 1 = Enables Interrupt Generation Line Code Violation / Counter Overflow Interrupt Enable 0 = Masks the LCV/OF function 1 = Enables Interrupt Generation Network Loop Code Detection Interrupt Enable 0 = Masks the NLCD function 1 = Enables Interrupt Generation Alarm Indication Signal Interrupt Enable 0 = Masks the AIS function 1 = Enables Interrupt Generation R/W D6 R/W 0 D5 FLSIE R/W 0 D4 LCV/OFIE R/W 0 D3 NLCDIE R/W 0 D2 AISIE R/W 0 56 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 29: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION CHANNEL 0-13 (0X04H-0XD4H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D1 RLOSIE Receiver Loss of Signal Interrupt Enable 0 = Masks the RLOS function 1 = Enables Interrupt Generation Quasi Random Signal Source Interrupt Enable 0 = Masks the QRPD function 1 = Enables Interrupt Generation R/W D0 QRPDIE R/W 0 NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the interrupt pin. TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION CHANNEL 0-13 (0X05H-0XD5H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 EQFLAG Equalizer Attenuation Flag The equalizer attenuation flag is always active regardless if the interrupt generation is disabled. This bit indicates the EQFLAG activity. An interrupt will not occur unless the EQFLAGE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = Equalizer Attenuation Flag is Set Digital Monitor Output The digital monitor output is always active regardless if the interrupt generation is disabled. This bit indicates the DMO activity. An interrupt will not occur unless the DMOIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = Transmit output driver has failures FIFO Limit Status The FIFO limit status is always active regardless if the interrupt generation is disabled. This bit indicates whether the RD/WR pointers are within 3-Bits. An interrupt will not occur unless the FLSIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = RD/WR FIFO pointers are within 3-Bits RO D6 DMO RO 0 D5 FLS RO 0 57 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION CHANNEL 0-13 (0X05H-0XD5H) Register Type REV. P1.0.5 NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the interrupt pin. BIT NAME FUNCTION Default Value (HW reset) 0 D4 LCV/OF Line Code Violation / Counter Overflow This bit serves a dual purpose. By default, this bit monitors the line code violation activity. However, if bit 7 in register 0xE5h is set to a "1", this bit monitors the overflow status of the internal LCV counter. An interrupt will not occur unless the LCV/OFIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = A line code violation, bipolar violation, or excessive zeros has occurred Network Loop Code Detection The network loop code detection is always active regardless if the interrupt generation is disabled. This bit indicates the NLCD activity. An interrupt will not occur unless the NLCDIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = Network loop code detected according to the mode selected in channel register 0x03h Alarm Indication Signal The alarm indication signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the AIS activity. An interrupt will not occur unless the AISIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = An all ones signal is detected Receiver Loss of Signal The receiver loss of signal detection is always active regardless if the interrupt generation is disabled. This bit indicates the RLOS activity. An interrupt will not occur unless the RLOSIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = An RLOS condition is present Quasi Random Pattern Detection The quasi random pattern detection is always active regardless if the interrupt generation is disabled. This bit indicates that a QRPD has been detected. An interrupt will not occur unless the QRPDIE is set to "1" in the channel register 0x04h and GIE is set to "1" in the global register 0xE0h. 0 = No Alarm 1 = A QRP is detected RO D3 NLCD RO 0 D2 AISD RO 0 D1 RLOS RO 0 D0 QRPD RO 0 58 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 31: MICROPROCESSOR REGISTER 0X06H BIT DESCRIPTION CHANNEL 0-13 (0X06H-0XD6H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 EQFLAGS Equalizer Attenuation Flag Status 0 = No change 1 = Change in status occurred DMOIS Digital Monitor Output Status 0 = No change 1 = Change in status occurred FIFO Limit Status 0 = No change 1 = Change in status occurred Line Code Violation / Overflow Status 0 = No change 1 = Change in status occurred Network Loop Code Detection Status 0 = No change 1 = Change in status occurred Alarm Indication Signal Status 0 = No change 1 = Change in status occurred Receiver Loss of Signal Status 0 = No change 1 = Change in status occurred Quasi Random Pattern Detection Status 0 = No change 1 = Change in status occurred RUR D6 RUR 0 D5 FLSIS RUR 0 D4 LCV/OFIS RUR 0 D3 NLCDIS RUR 0 D2 AISDIS RUR 0 D1 RLOSIS RUR 0 D0 QRPDIS RUR 0 NOTE: Any change in status will generate an interrupt (if enabled in channel register 0x04h and GIE is set to "1" in the global register 0xE0h). The status registers are reset upon read (RUR). 59 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 32: MICROPROCESSOR REGISTER 0X07H BIT DESCRIPTION CHANNEL 0-13 (0X07H-0XD7H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) D7 D6 Reserved FLSDET This Register Bit is Not Used. FIFO LIMIT STATUS DETECT The FLSDET is used to determine whether the receiver or transmitter FIFO has reached its limit status. If both FIFOs reach their limit capacity, this bit will be set to "1". 0 = Receive JA 1 = Transmit JA Cable Loss Indication This 6-Bit binary word indicates the cable attenuation on the receiver inputs RTIP/RRING within 1dB with Bit 5 being the MSB. RO 0 D5 D4 D3 D2 D1 D0 CLOS5 CLOS4 CLOS3 CLOS2 CLOS1 CLOS0 RO 0 TABLE 33: MICROPROCESSOR REGISTER 0X08H BIT DESCRIPTION CHANNEL 0-13 (0X08H-0XD8H) Register Type Default Value (HW reset) 0 0 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Reserved 1SEG6 1SEG5 1SEG4 1SEG3 1SEG2 1SEG1 1SEG0 This Register Bit is Not Used Arbitrary Pulse Generation The transmit output pulse is divided into 8 individual segments. This register is used to program the first segment which corresponds to the overshoot of the pulse amplitude. There are four segments for the top portion of the pulse and four segments for the bottom portion of the pulse. Segment number 5 corresponds to the undershoot of the pulse. The MSB of each segment is the sign bit. Bit 6 = 0 = Negative Direction Bit 6 = 1 = Positive Direction X R/W 60 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 34: MICROPROCESSOR REGISTER 0X09H BIT DESCRIPTION CHANNEL 0-13 (0X09H-0XD9H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 2SEG[6:0] This Register Bit is Not Used Segment Number Two, Same Description as Register 0x08h X R/W TABLE 35: MICROPROCESSOR REGISTER 0X0AH BIT DESCRIPTION CHANNEL 0-13 (0X0AH-0XDAH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 3SEG[6:0] This Register Bit is Not Used Segment Number Three, Same Description as Register 0x08h X R/W TABLE 36: MICROPROCESSOR REGISTER 0X0BH BIT DESCRIPTION CHANNEL 0-13 (0X0BH-0XDBH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 4SEG[6:0] This Register Bit is Not Used Segment Number Four, Same Description as Register 0x08h X R/W TABLE 37: MICROPROCESSOR REGISTER 0X0CH BIT DESCRIPTION CHANNEL 0-13 (0X0CH-0XDCH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 5SEG[6:0] This Register Bit is Not Used Segment Number Five, Same Description as Register 0x08h X R/W 61 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 38: MICROPROCESSOR REGISTER 0X0DH BIT DESCRIPTION CHANNEL 0-13 (0X0DH-0XDDH) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 D7 D[6:0] Reserved 6SEG[6:0] This Register Bit is Not Used Segment Number Six, Same Description as Register 0x08h X R/W TABLE 39: MICROPROCESSOR REGISTER 0X0EH BIT DESCRIPTION CHANNEL 0-13 (0X0EH-0XDEH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 7SEG[6:0] This Register Bit is Not Used Segment Number Seven, Same Description as Register 0x08h X R/W TABLE 40: MICROPROCESSOR REGISTER 0X0FH BIT DESCRIPTION CHANNEL 0-13 (0X0FH-0XDFH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 D[6:0] Reserved 8SEG[6:0] This Register Bit is Not Used Segment Number Eight, Same Description as Register 0x08h X R/W 62 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION GLOBAL REGISTER (0XE0H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 SR/DR Single Rail/Dual Rail Mode This bit sets the LIU to receive and transmit digital data in a single rail or a dual rail format. 0 = Dual Rail Mode 1 = Single Rail Mode Automatic Transmit All Ones If ATAOS is selected, an all ones pattern will be transmitted on any channel that experiences an RLOS condition. If an RLOS condition does not occur, TAOS will remain inactive. 0 = Disabled 1 = Enabled Receive Clock Data 0 = RPOS/RNEG data is updated on the rising edge of RCLK 1 = RPOS/RNEG data is updated on the falling edge of RCLK Transmit Clock Data 0 = TPOS/TNEG data is sampled on the falling edge of TCLK 1 = TPOS/TNEG data is sampled on the rising edge of TCLK Data Polarity 0 = Transmit input and receive output data is active "High" 1 = Transmit input and receive output data is active "Low" This Register Bit is Not Used Global Interrupt Enable The global interrupt enable is used to enable/disable all interrupt activity for all 14 channels. This bit must be set "High" for the interrupt pin to operate. 0 = Disable all interrupt generation 1 = Enable interrupt generation to the individual channel registers Software Reset Writing a "1" to this bit for more than 10S initiates a device reset for all internal circuits except the microprocessor register bits. To reset the registers to their default setting, use the Hardware Reset pin (See the pin description for more details). R/W D6 ATAOS R/W 0 D5 RCLKE R/W 0 D4 TCLKE R/W 0 D3 DATAP R/W 0 D2 D1 Reserved GIE R/W R/W 0 0 D0 SRESET R/W 0 63 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 42: MICROPROCESSOR REGISTER 0XE1H BIT DESCRIPTION GLOBAL REGISTER (0XE1H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 0 0 0 D7 D6 D5 D4 Reserved Reserved GAUGE1 GAUGE0 This Register Bit is Not Used This Register Bit is Not Used Wire Gauge Select 00 = 22 and 24 gauge 01 = 22 gauge 10 = 24 gauge 11 = 26 gauge This Register Bit is Not Used Receiver Output Mute Enable If RxMUTE is selected, RPOS/RNEG will be pulled "Low" for any channel that experiences an RLOS condition. If an RLOS condition does not occur, RxMUTE will remain inactive. 0 = Disabled 1 = Enabled Extended Loss of Zeros The number of zeros required to declare a Digital Loss of Signal is extended to 4,096. 0 = Normal Operation 1 = Enables the EXLOS function In Circuit Testing 0 = Normal Operation 1 = Sets all output pins to "High" impedance for in circuit testing R/W R/W R/W D3 D2 Reserved RxMUTE R/W R/W 0 0 D1 EXLOS R/W 0 D0 ICT R/W 0 TABLE 43: MICROPROCESSOR REGISTER 0XE2H BIT DESCRIPTION GLOBAL REGISTER (0XE2H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 Reserved This Register Bit is Not Used R/W 64 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY GLOBAL REGISTER (0XE2H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D6 RxTCNTL Receive Termination Select Control This bit sets the LIU to control the RxTSEL function with either the individual channel register bit or the global hardware pin. 0 = Control of the receive termination is set to the register bits 1 = Control of the receive termination is set to the hardware pin Equalizer Attenuation Flag EQFLAG[5:0] is used to generate an interrupt condition for an RLOS other than the default setting described in the datasheet. A desired value can be programmed into this register. If EQFLAGE is enabled in register 0x04h and if this 6-Bit binary word is equal to the 6-Bit cable loss indicator, an interrupt will be generated. R/W D5 D4 D3 D2 D1 D0 EQFLAG5 EQFLAG4 EQFLAG3 EQFLAG2 EQFLAG1 EQFLAG0 R/W 0 0 0 0 0 0 TABLE 44: MICROPROCESSOR REGISTER 0XE3H BIT DESCRIPTION GLOBAL REGISTER (0XE3H) Register Type Default Value (HW reset) 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 Reserved Reserved Reserved Reserved SL1 SL0 This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used Slicer Level Select 00 = 50% 01 = 45% 10 = 55% 11 = 68% Equalizer Gain Control 00 = Normal 01 = Reduce Gain by 1dB 10 = Reduce Gain by 3dB 11 = Normal R/W R/W R/W R/W R/W D1 D0 EQG1 EQG0 R/W 0 65 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 45: MICROPROCESSOR REGISTER 0XE4H BIT DESCRIPTION GLOBAL REGISTER (0XE4H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 0 D7 D6 MclkT1out1 MCLKT1OUT Select MclkT1out0 MclkT1out[1:0] is used to program the MCLKT1out pin. By default, the output clock is 1.544MHz. 00 = 1.544MHz 01 = 3.088MHz 10 = 6.176MHz 11 = 12.352MHz MclkE1out1 MCLKE1OUT Select MclkE1out0 MclkE1out[1:0] is used to program the MCLKE1out pin. default, the output clock is 2.048MHz. 00 = 2.048MHz 01 = 4.096MHz 10 = 8.192MHz 11 = 16.384MHz Reserved Reserved Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used R/W D5 D4 R/W By 0 0 D3 D2 D1 D0 R/W R/W R/W R/W 0 0 0 0 TABLE 46: MICROPROCESSOR REGISTER 0XE5H BIT DESCRIPTION GLOBAL REGISTER (0XE5H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D7 LCV/OFLW Line Code Violation / Counter Overflow Monitor Select This bit is used to select the monitoring activity between the LCV and the counter overflow status. When the 16-bit LCV counter saturates, the counter overflow condition is activated. By default, the LCV activity is monitored by bit D4 in register 0x05h. 0 = Monitoring LCV 1 = Monitoring the counter overflow status CNTRDEN Line Code Violation Counter Read Enable This bit enables the 16-bit LCV counter contents to be read from bits D[7:0] in register 0xE8h. If a counter reaches full scale, it saturates and remains at FFFFh until a reset is initiated in register 0xE6h. By default, the LCV counter readback function is disabled. 0 = Disabled 1 = Enables the 16-bit LCV Counters for Readback R/W D6 R/W 0 66 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY GLOBAL REGISTER (0XE5H) Register Type Default Value (HW reset) 0 0 0 0 0 0 BIT NAME FUNCTION D5 D4 D3 D2 D1 D0 Reserved Reserved LCVCH3 LCVCH2 LCVCH1 LCVCH0 This Register Bit is Not Used This Register Bit is Not Used Line Code Violation Counter Select These bits are used to select which channel is to be addressed for reading the contents in register 0xE8h. It is also used to address the counter for a given channel when performing an update or reset on a per channel basis. By default, Channel 0 is selected. 0000 = None 0001 = Channel 0 0010 = Channel 1 0011 = Channel 2 0100 = Channel 3 0101 = Channel 4 0110 = Channel 5 0111 = Channel 6 1000 = Channel 7 1001 = Channel 8 1010 = Channel 9 1011 = Channel 10 1100 = Channel 11 1101 = Channel 12 1110 = Channel 13 R/W R/W R/W TABLE 47: MICROPROCESSOR REGISTER 0XE6H BIT DESCRIPTION GLOBAL REGISTER (0XE6H) Register Type Default Value (HW reset) 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 Reserved Reserved Reserved allRST This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used LCV Counter Reset for All Channels This bit is used to reset all internal LCV counters to their default state 0000h. This bit must be set to "1" for 1S. 0 = Normal Operation 1 = Resets all Counters R/W R/W R/W R/W 67 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY GLOBAL REGISTER (0XE6H) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 D3 allUPDATE LCV Counter Update for All Channels This bit is used to latch the contents of all 14 counters into holding registers so that the value of each counter can be read. The channel is addressed by using bits D[3:0] in register 0xE5h. 0 = Normal Operation 1 = Updates all Counters BYTEsel LCV Counter Byte Select This bit is used to select the MSB or LSB for Reading the contents of the LCV counter for a given channel. The channel is addressed by using bits D[3:0] in register 0xE5h. By default, the LSB byte is selected. 0 = Low Byte 1 = High Byte R/W D2 R/W 0 D1 chUPDATE LCV Counter Update Per Channel This bit is used to latch the contents of the counter for a given channel into a holding register so that the value of the counter can be read. The channel is addressed by using bits D[3:0] in register 0xE5h. 0 = Normal Operation 1 = Updates the Selected Channel Reserved LCV Counter Reset Per Channel This bit is used to reset the LCV counter of a given channel to its default state 0000h. The channel is addressed by using bits D[3:0] in register 0xE5h. This bit must be set to "1" for 1S. 0 = Normal Operation 1 = Resets the Selected Channel R/W 0 D0 R/W 0 TABLE 48: MICROPROCESSOR REGISTER 0XE7H BIT DESCRIPTION GLOBAL REGISTER (0XE7H) Register Type Default Value (HW reset) 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 Reserved Reserved Reserved Reserved Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used This Register Bit is Not Used R/W R/W R/W R/W R/W R/W 68 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY GLOBAL REGISTER (0XE7H) Register Type Default Value (HW reset) 0 0 BIT NAME FUNCTION D1 D0 Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used R/W R/W TABLE 49: MICROPROCESSOR REGISTER 0XE8H BIT DESCRIPTION GLOBAL REGISTER (0XE8H) Register Type Default Value (HW reset) 0 0 0 0 0 0 0 0 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 LCVCNT7 LCVCNT6 LCVCNT5 LCVCNT4 LCVCNT3 LCVCNT2 LCVCNT1 LCVCNT0 Line Code Violation Byte Contents These bits contain the LCV counter contents of the Byte selected by bit D2 in register 0xE6h for a given channel. The channel is addressed by using bits D[3:0] in register 0xE5h. By default, the contents contain the LSB, however no channel is selected.. R/W 69 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY CLOCK SELECT REGISTER REV. P1.0.5 The input clock source is used to generate all the necessary clock references internally to the LIU. The microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits in register 0xE9h. Therefore, if the clock selection bits are being programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is important to "Not" write to any other bit location within the same register while selecting the input/output clock frequency. For best results, register 0xE9h can be broken down into two sub-registers with the MSB being bits D[7:4] and the LSB being bits D[3:0] as shown in Figure 42. Note: Bits D[7:6] are reserved. FIGURE 42. REGISTER 0XE9H SUB REGISTERS MSB D7 D6 D5 D4 D3 D2 LSB D1 D0 ALLT1/E1, CLKCNTL Clock Selection Bits Programming Examples: Example 1: Changing bits D[7:4] If bits D[7:4] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 2: Changing bits D[3:0] If bits D[3:0] are the only values within the register that will change in a WRITE process, the microprocessor only needs to initiate ONE write operation. Example 3: Changing bits within the MSB and LSB In this scenario, one must initiate TWO write operations such that the MSB and LSB do not change within ONE write cycle. It is recommended that the MSB and LSB be treated as two independent sub-registers. One can either change the clock selection (LSB) and then change bits D[5:4] (MSB) on the SECOND write, or viceversa. No order or sequence is necessary. TABLE 50: MICROPROCESSOR REGISTER 0XE9H BIT DESCRIPTION GLOBAL REGISTER (0XE9H) Register Type Default Value (HW reset) 0 0 BIT NAME FUNCTION D7 D6 Reserved Reserved This Register Bit is Not Used This Register Bit is Not Used R/W R/W 70 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY GLOBAL REGISTER (0XE9H) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D5 ALLT1/E1 T1/E1 Control This bit is used to reduce system noise and power consumption. If the ALL T1/E1 mode is enabled, all output clock references (excluding the 8kHzout in E1 mode only) are internally shut off. By default, the ALL T1/E1 mode is enabled. 0 = Enabled (reduce clock switching and power consumption) 1 = Disabled (all clock references are available) Transmit Clock Control This bit is used to select the transmit output activity at TTIP/TRING when TCLK is either pulled "Low", pulled "High", or missing. 0 = Transmit All Zeros 1 = TAOS (Transmit All Ones) Clock Input Select CLKSEL[3:0] is used to select the input clock source used as the internal timing reference. 0000 = 2.048 MHz 0001 = 1.544 MHz 0010 = 8 kHz 0011 = 16 kHz 0100 = 56 kHz 0101 = 64 kHz 0110 = 128 kHz 0111 = 256 kHz 1000 = 4.096 Mhz 1001 = 3.088 Mhz 1010 = 8.192 Mhz 1011 = 6.176 Mhz 1100 = 16.384 Mhz 1101 = 12.352 Mhz 1110 = 2.048 Mhz 1111 = 1.544 Mhz R/W D4 TCLKCNL R/W 0 D3 D2 D1 D0 CLKSEL3 CLKSEL2 CLKSEL1 CLKSEL0 R/W 0 0 0 0 71 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 51: MICROPROCESSOR REGISTER 0XEAH BIT DESCRIPTION GLOBAL REGISTER (0XEAH) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 0 D7 GCHIS7 Global Channel Interrupt Status for Channel 7 0 = No interrupt activity from channel 7 1 = Interrupt was generated from channel 7 Global Channel Interrupt Status for Channel 6 0 = No interrupt activity from channel 6 1 = Interrupt was generated from channel 6 Global Channel Interrupt Status for Channel 5 0 = No interrupt activity from channel 5 1 = Interrupt was generated from channel 5 Global Channel Interrupt Status for Channel 4 0 = No interrupt activity from channel 4 1 = Interrupt was generated from channel 4 Global Channel Interrupt Status for Channel 3 0 = No interrupt activity from channel 3 1 = Interrupt was generated from channel 3 Global Channel Interrupt Status for Channel 2 0 = No interrupt activity from channel 2 1 = Interrupt was generated from channel 2 Global Channel Interrupt Status for Channel 1 0 = No interrupt activity from channel 1 1 = Interrupt was generated from channel 1 Global Channel Interrupt Status for Channel 0 0 = No interrupt activity from channel 0 1 = Interrupt was generated from channel 0 RUR D6 GCHIS6 RUR 0 D5 GCHIS5 RUR 0 D4 GCHIS4 RUR 0 D3 GCHIS3 RUR 0 D2 GCHIS2 RUR 0 D1 GCHIS1 RUR 0 D0 GCHIS0 RUR 0 TABLE 52: MICROPROCESSOR REGISTER 0XEBH BIT DESCRIPTION GLOBAL REGISTER (0XEBH) Register Type Default Value (HW reset) 0 0 0 BIT NAME FUNCTION D7 D6 D5 Reserved Reserved GCHIS13 This Register Bit is Not Used This Register Bit is Not Used Global Channel Interrupt Status for Channel 13 0 = No interrupt activity from channel 13 1 = Interrupt was generated from channel 13 RUR RUR RUR 72 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY GLOBAL REGISTER (0XEBH) Register Type Default Value (HW reset) 0 BIT NAME FUNCTION D4 GCHIS12 Global Channel Interrupt Status for Channel 12 0 = No interrupt activity from channel 12 1 = Interrupt was generated from channel 12 Global Channel Interrupt Status for Channel 11 0 = No interrupt activity from channel 11 1 = Interrupt was generated from channel 11 Global Channel Interrupt Status for Channel 10 0 = No interrupt activity from channel 10 1 = Interrupt was generated from channel 10 Global Channel Interrupt Status for Channel 9 0 = No interrupt activity from channel 9 1 = Interrupt was generated from channel 9 Global Channel Interrupt Status for Channel 8 0 = No interrupt activity from channel 8 1 = Interrupt was generated from channel 8 RUR D3 GCHIS11 RUR 0 D2 GCHIS10 RUR 0 D1 GCHIS9 RUR 0 D0 GCHIS8 RUR 0 TABLE 53: E1 ARBITRARY SELECT E1 ARBITRARY SELECT REGISTER (0XF4H) Register Type Default Value (HW reset) BIT NAME FUNCTION D[7:1] D0 Reserved E1arben E1 Arbitrary Pulse Enable This bit is used to enable the Arbitrary Pulse Generators for shaping the transmit pulse shape when E1 mode is selected. If this bit is set to "1", all 14 channels will be configured for the Arbitrary Mode. However, each channel is individually controlled by programming the channel registers 0xn8 through 0xnF, where n is the number of the channel. "0" = Disabled (Normal E1 Pulse Shape ITU G.703) "1" = Arbitrary Pulse Enabled R/W 0 73 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY DEVICE "ID" REGISTER (0XFEH) Register Type REV. P1.0.5 BIT NAME FUNCTION Default Value (HW reset) 1 1 1 1 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Device "ID" The device "ID" of the XRT83SL314 short haul LIU is 0xFEh. Along with the revision "ID", the device "ID" is used to enable software to identify the silicon adding flexibility for system control and debug. RO Microprocessor Register 0xFEh Bit Description TABLE 54: MICROPROCESSOR REGISTER 0XFFH BIT DESCRIPTION REVISION "ID" REGISTER (0XFFH) Register Type Default Value (HW reset) 0 0 0 0 0 0 0 1 BIT NAME FUNCTION D7 D6 D5 D4 D3 D2 D1 D0 Revision "ID" The revision "ID" of the XRT83SL314 LIU is used to enable software to identify which revision of silicon is currently being tested. The revision "ID" for the first revision of silicon will be 0x01h. RO 74 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 55: ABSOLUTE MAXIMUM RATINGS Storage Temperature Operating Temperature Supply Voltage Vin -65C to +150C -40C to +85C -0.5V to +3.8V -0.5V to +5.5V ELECTRICAL CHARACTERISTICS TABLE 56: DC DIGITAL INPUT AND OUTPUT ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage IOH=2.0mA Output Low Voltage IOL=2.0mA Input Leakage Current Input Capacitance Output Lead Capacitance SYMBOL VDD VIH VIL VOH VOL IL CI CL MIN 3.13 2.0 -0.5 2.4 TYP 3.3 5.0 25 0.4 10 MAX 3.46 5.0 0.8 UNITS V V V V V A pF pF NOTE: Input leakage current excludes pins that are internally pulled "Low" or "High" TABLE 57: AC ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER MCLKin Clock Duty Cycle MCLKin Clock Tolerance SYMBOL MIN 40 TYP 50 MAX 60 UNITS % ppm 75 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 58: POWER CONSUMPTION VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED MODE E1 SUPPLY VOLTAGE 3.3V IMPEDANCE 75 RECEIVER 1:1 TRANSMITTER 1:2 TYP TBD TBD TBD TBD TBD TBD MAX UNIT mW REV. P1.0.5 TEST CONDITION 50% ones 100% ones 50% ones 100% ones 50% ones 100% ones E1 3.3V 120 1:1 1:2 - mW T1 3.3V 100 1:1 1:2 - mW TABLE 59: E1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul with cable loss) 32 MIN TYP MAX UNIT TEST CONDITION 15 12.5 11 24 - - dB % ones dB Cable attenuation @ 1024kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 with -18dB interference signal added. Input Impedance Input Jitter Tolerance 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude - 13 - k 37 0.2 - - UIp-p UIp-p ITU-G.823 - 36 - -0.5 kHz dB ITU-G.736 76 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY TABLE 59: E1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER MIN TYP MAX UNIT TEST CONDITION Jitter Attenuator Corner Frequency JABW = 0 JABW = 1 Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz - 10 1.5 - Hz Hz ITU-G.736 14 20 16 - - dB dB dB ITU-G.703 TABLE 60: T1 RECEIVER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER Receiver Loss of Signal Number of consecutive zeros before RLOS is declared Input signal level at RLOS RLOS clear Receiver Sensitivity (short haul with cable loss) Input Impedance Input Jitter Tolerance 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 160 175 190 MIN TYP MAX UNIT TEST CONDITION 15 12.5 12 - 24 13 - dB % ones dB k Cable attenuation @ 772kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 100 termination. 138 0.4 - - UIp-p UIp-p AT&T Pub 62411 - 9.8 6 0.1 - kHz dB Hz TR-TSY-000499 AT&T Pub 62411 - 20 25 25 - dB dB dB 77 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT PRELIMINARY TABLE 61: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER AMI Output Pulse Amplitude 75 120 Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio Jitter Added by the Transmitter Output Output Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz MIN TYP MAX UNIT REV. P1.0.5 TEST CONDITION 2.13 2.70 224 0.95 0.95 - 2.37 3.00 244 0.025 2.60 3.30 264 1.05 1.05 0.05 V V ns 1:2 Transformer ITU-G.703 ITU-G.703 UIp-p Broad Band with jitter free TCLK applied to the input. 8 14 10 - - dB dB dB ETSI 300 166, CHPTT TABLE 62: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS VDD=3.3V 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER AMI Output Pulse Amplitude Output Pulse Width Output Pulse Width Imbalance Output Pulse Amplitude Imbalance Jitter Added by the Transmitter Output Output Return Loss 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz MIN 2.4 338 TYP 3.0 350 0.025 MAX 3.6 362 20 200 0.05 mV UIp-p UNIT V ns TEST CONDITION 1:2 Transformer measured at DSX-1 ANSI T1.102 ANSI T1.102 ANSI T1.102 Broad Band with jitter free TCLK applied to the input. - 15 15 15 - dB dB dB 78 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY PACKAGE 304 LEAD TBGA OPERATING TEMPERATURE RANGE -400C to +850C ORDERING INFORMATION PRODUCT NUMBER XRT83SL314IB PACKAGE DIMENSIONS (DIE DOWN) 22 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L A1 Feature/Mark D D1 M N P R T U V W Y AA AB AC D1 D (A1 corner feature is mfger option) P SEATING PLANE e A1 A b A2 Note: The control dimension is in millimeter. INCHES MIN MAX 0.051 0.067 0.018 0.028 0.031 0.071 0.004 0.012 1.213 1.228 1.100 BSC 0.024 0.035 0.050 BSC MILLIMETERS MIN MAX 1.30 1.70 0.45 0.70 0.80 1.80 0.10 0.30 30.80 31.20 27.94 BSC 0.60 0.90 1.27 BSC SYMBOL A A1 A2 P D D1 b e 79 XRT83SL314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT REV. P1.0.5 PRELIMINARY REVISION HISTORY REVISION # P1.0.0 P1.0.1 P1.0.2 P1.0.3 P1.0.4 P1.0.5 DATE 01/22/03 01/28/03 02/14/03 03/27/03 09/19/03 11/12/03 DESCRIPTION First release of the 14-Channel LIU Preliminary Datasheet Added the Motorola 68K asynchronous Mode Timing Edited the Microprocessor Timing Specifications Added the 16-bit LCV Counter Details for Revision B Silicon Changed the Microprocessor Access Timing Parameters Added new E1 arbitrary pulse feature. Added descriptions to the global registers. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet November 2003. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 80 |
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